IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
R
Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When V
reaches the voltage at which portions
CC
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a
self-generated internal timer. This nominal 1-MHz timer is
subject to variations with process, temperature and power
supply. As shown in
Table
1, five configuration mode
choices are available as determined by the input levels of
three mode pins; M0, M1 and M2.
Table 1: Configuration Mode Choices
M0 M1 M2 CCLK
Mode
0
0
0 output
Master
Bit Serial
0
0
1 output
Master
Byte Wide Addr. = 0000 up
0
1
0 —
reserved
0
1
1 output
Master
Byte Wide Addr. = FFFF down
1
0
0 —
reserved
1
0
1 output
Peripheral Byte Wide
1
1
0 —
reserved
1
1
1 input
Slave
Bit Serial
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
INIT Output = Low
Initialization
Power-On
Time Delay
Clear
RESET
Configuration
No
Active
Memory
Power-On Delay is
14
2
Cycles for Non-Master Mode—11 to 33 ms
16
2
Cycles for Master Mode—43 to 130 ms
Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.
November 9, 1998 (Version 3.1)
XC3000 Series Field Programmable Gate Arrays
In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning
of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An FPGA with mode lines selecting a
Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
be ready even if the master is very fast, and the slave(s)
very slow.
Figure 20
of Initialization, the device enters the Clear state where it
clears the configuration memory. The active Low,
open-drain initialization signal INIT indicates when the Ini-
tialization and Clear states are complete. The FPGA tests
for the absence of an external active Low RESET before it
makes a final sample of the mode lines and enters the Con-
figuration state. An external wired-AND of one or more INIT
pins can be used to control configuration by the assertion of
the active-Low RESET of a master mode device or to sig-
nal a processor that the FPGAs are not yet initialized.
Data
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
During configuration, the XC3000A, XC3000L, XC3100A,
and XC3100L devices check the bit-stream format for stop
bits in the appropriate positions. Any error terminates the
configuration and pulls INIT Low.
Active RESET
Test
Configuration
Mode Pins
Program Mode
Low on DONE/PROGRAM and RESET
Clear Is
~ 200 Cycles for the XC3020A—130 to 400 s
~ 250 Cycles for the XC3030A—165 to 500 s
~ 290 Cycles for the XC3042A—195 to 580 s
~ 330 Cycles for the XC3064A—220 to 660 s
~ 375 Cycles for the XC3090A—250 to 750 s
shows the state sequences. At the end
Power Down
No HDC, LDC
or Pull-Up
PWRDWN
Inactive
PWRDWN
Active
Operational
Start-Up
Mode
Active RESET
Operates on
User Logic
X3399
7-19
7