IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
R
XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad active and valid
(fast)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042L)
RESET Pad to Registered In
(Q)
RESET Pad to output pad
(fast)
(slew-rate limited)
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T
, T
, and T
are 3 ns higher for XTL2 when the pin is configured as a user input.
PID
PTG
PICK
November 9, 1998 (Version 3.1)
XC3000 Series Field Programmable Gate Arrays
Speed Grade
Symbol
3
T
PID
T
PTG
4
T
IKRI
1
T
PICK
7
T
OKPO
7
T
OKPO
10
T
OPF
10
T
OPS
9
T
TSHZ
9
T
TSHZ
8
T
TSON
8
T
TSON
5
T
OOK
6
T
OKO
11
T
IOH
12
T
IOL
F
CLK
13
T
RRI
15
T
RPO
15
T
RPO
-8
Min
Max
Units
5.0
ns
24.0
ns
6.0
ns
22.0
ns
12.0
ns
28.0
ns
9.0
ns
25.0
ns
12.0
ns
28.0
ns
16.0
ns
32.0
ns
7
12.0
ns
0
ns
5.0
ns
5.0
ns
80.0
MHz
25.0
ns
35.0
ns
51.0
ns
7-51