XC3030A-7PC84C Xilinx Inc, XC3030A-7PC84C Datasheet - Page 27

• Manufacturer Part Number: XC3030A-7PC84C
• Description: IC LOGIC CL ARRAY 3000GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC3000A/Lr

Specifications of XC3030A-7PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 22176
• Number Of I /o: 74
• Number Of Gates: 2000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1018

Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again
November 9, 1998 (Version 3.1)
Figure 27: Peripheral Mode Circuit Diagram
CONTROL
SIGNALS
R
REPROGRAM
+5 V
ADDRESS
BUS
Product Obsolete or Under Obsolescence
ADDRESS
DECODE
LOGIC
DATA
OC
BUS
8
D0–7
D0–7
CS1
CS2
WS
RDY/BUSY
INIT
D/P
RESET
CS0
M0
FPGA
XC3000 Series Field Programmable Gate Arrays
I/O PINS
*
OTHER
M1 PWR
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
when the byte-wide input buffer has transferred its informa-
tion into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
DOUT
DWN
CCLK
HDC
LDC
M2
GENERAL-
PURPOSE
USER I/O
PINS
5 k
+5 V
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
*
ACTIVATED, A
5-k RESISTOR IS
REQUIRED IN SERIES
WITH M1
IF READBACK IS
X5991
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