IC LOGIC CL ARRAY 3000GAT 84PLCC

XC3030A-7PC84C

Manufacturer Part NumberXC3030A-7PC84C
DescriptionIC LOGIC CL ARRAY 3000GAT 84PLCC
ManufacturerXilinx Inc
SeriesXC3000A/L
XC3030A-7PC84C datasheet
 


Specifications of XC3030A-7PC84C

Number Of Labs/clbs100Total Ram Bits22176
Number Of I /o74Number Of Gates2000
Voltage - Supply4.75 V ~ 5.25 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case84-LCC (J-Lead)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantNumber Of Logic Elements/cells-
Other names122-1018  
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Product Obsolete or Under Obsolescence
XC3000 Series Field Programmable Gate Arrays
1.00
0.80
0.60
0.40
0.20
– 55
– 40
– 20
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
300
250
200
150
100
XC3100A-3
50
XC3000A--6
0
CLB Levels:
4 CLBs
3 CLBs
2 CLBs
Gate Levels:
(4-16)
(3-12)
(2-8)
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
7-36
TYPICAL COMMERCIAL
(+ 5.0 V, 25 C)
TYPICAL MILITARY
0
25
40
70
TEMPERATURE ( C)
Power
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated V
rounding the logic array provides power to the I/O drivers.
An independent matrix of V
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all internal logic, pro-
viding the external package power pins are all connected
1 CLB
Toggle
and appropriately decoupled. Typically a 0.1- F capacitor
(1-4)
Rate
connected near the V
X7065
quate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
SPECIFIED WORST-CASE VALUES
80
100
125
X6094
and ground ring sur-
CC
and groundlines supplies the
CC
and ground pins will provide ade-
CC
November 9, 1998 (Version 3.1)
R