A80960JF3V25 Intel, A80960JF3V25 Datasheet - Page 21

• Manufacturer Part Number: A80960JF3V25
• Description: IC MPU I960JF 3.3V 25MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960JF3V25

• Processor Type: i960
• Features: JF suffix, 32-Bit, 4K Cache
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819540

Datasheet
Table 8. Pin Description—External Bus Signals (Sheet 4 of 4)
Table 9.
Pin Description—Processor Control Signals, Test Signals, and Power (Sheet 1 of 2)
RESET#
HOLDA
BSTAT
STEST
CLKIN
NAME
NAME
FAIL#
TCK
TDI
TYPE
TYPE
R(Q)
P(Q)
H(Q)
H(Q)
H(1)
R(0)
R(0)
P(0)
A(L)
S(L)
P(1)
S(L)
O
O
O
I
I
I
I
I
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. The processor may grant HOLD requests and enter
the T
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see i960
Arbitration logic may examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
CLOCK INPUT provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK#/ONCE#,
STEST and HOLD.
The RESET# pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET# must be asserted a minimum of 10,000
CLKIN cycles with V
asserted for a minimum of 15 cycles.
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
FAIL indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL# is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
0 = self test failed
1 = self test passed
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
• When self-test passes, the processor deasserts FAIL# and begins operation
• When self-test fails, the processor asserts FAIL# and then stops executing.
from user code.
h
state during reset and while halted as well as during regular operation.
CC
and CLKIN stable. On a warm reset, RESET# should be
®
Jx Microprocessor Developer’s Manual (272483).
DESCRIPTION
DESCRIPTION
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