A80960JF3V25 Intel, A80960JF3V25 Datasheet - Page 4

• Manufacturer Part Number: A80960JF3V25
• Description: IC MPU I960JF 3.3V 25MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960JF3V25

• Processor Type: i960
• Features: JF suffix, 32-Bit, 4K Cache
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819540

Contents
Figures
4
1
2
3
4
5
6
7
8
9
10 A.C. Test Load............................................................................................................................ 45
11 Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) .......................... 46
12 Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5 V Signals) ............................. 46
13 Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD .................................................... 47
14 T
15 T
16 T
17 I
18 80960JA/JF I
19 80960JD I
20 80960JD I
21 80960JC I
22 80960JC I
23 80960JS I
24 80960JS I
25 CLKIN Waveform........................................................................................................................ 53
26 T
27 T
28 T
29 T
30 T
31 T
32 T
33 DT/R# and DEN# Timings Waveform......................................................................................... 56
34 TCK Waveform ........................................................................................................................... 57
35 T
36 T
37 T
38 T
39 80960JS/JC/JT Device Identification Register Fields ................................................................. 60
40 80960JD Device Identification Register Fields ........................................................................... 61
41 80960JA/JF Device Identification Register Fields ...................................................................... 62
42 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus................................. 69
43 Burst Read and Write Transactions Without Wait States, 32-Bit Bus ........................................ 70
44 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus .................................................. 71
45 Burst Read and Write Transactions Without Wait States, 8-Bit Bus .......................................... 72
46 Burst Read and Write Transactions With 1, 0 Wait States
47 Double Word Read Bus Request, Misaligned One Byte From
80960Jx Microprocessor Package Options .................................................................................. 7
80960Jx Block Diagram.............................................................................................................. 10
132-Lead Pin Grid Array Top View-Pins Facing Down............................................................... 23
132-Lead Pin Grid Array Bottom View-Pins Facing Up .............................................................. 24
132-Lead PQFP - Top View ....................................................................................................... 27
196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down ............................................ 30
196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up ........................................... 31
VCC5 Current-Limiting Resistor ................................................................................................. 36
VCCPLL Lowpass Filter ............................................................................................................. 37
and Extra Tr State on Read, 16-Bit Bus ..................................................................................... 73
Quad Word Boundary, 32-Bit Bus, Little Endian ........................................................................ 74
CC
LX
LX
LX
OV1
OF
IS1
IS2
IS3
IS4
LX
BSIS1
BSOV1
BSOV2
BSIS2
, T
Active (Power Supply) vs. Frequency–80960JA/JF ............................................................. 49
vs. AD Bus Load Capacitance–80960JS/JC/JT (3.3 V Signals) ......................................... 47
vs. AD Bus Load Capacitance–80960JS/JC/JT (5 V Signals) ............................................ 48
vs. AD Bus Load Capacitance–80960JA/JF/JD................................................................... 48
Output Float Waveform ....................................................................................................... 54
and T
and T
and T
and T
Output Delay Waveform .................................................................................................... 53
LXL
and T
and T
and T
and T
and T
CC
CC
CC
CC
CC
CC
IH1
IH2
IH3
IH4
BSIH1
BSIH2
CC
Active (Power Supply) vs. Frequency ................................................................... 52
Active (Thermal) vs. Frequency ............................................................................ 52
Active (Power Supply) vs. Frequency ................................................................... 50
Active (Thermal) vs. Frequency ............................................................................ 50
Active (Power Supply) vs. Frequency ................................................................... 51
Active (Thermal) vs. Frequency ............................................................................ 51
BSOF1
BSOF2
Input Setup and Hold Waveform .......................................................................... 54
Input Setup and Hold Waveform .......................................................................... 54
Input Setup and Hold Waveform .......................................................................... 55
Input Setup and Hold Waveform .......................................................................... 55
LXA
Active (Thermal) vs. Frequency ....................................................................... 49
Input Setup and Hold Waveforms................................................................. 57
Input Setup and Hold Waveform................................................................... 58
Relative Timings Waveform ........................................................................ 56
Output Delay and Output Float Waveform ................................................. 57
Output Delay and Output Float Waveform ................................................. 58
Datasheet