A80960JF3V25 Intel, A80960JF3V25 Datasheet - Page 37

• Manufacturer Part Number: A80960JF3V25
• Description: IC MPU I960JF 3.3V 25MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960JF3V25

• Processor Type: i960
• Features: JF suffix, 32-Bit, 4K Cache
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819540

4.5
Datasheet
Table 19. VDIFF Parameters
Figure 9. VCCPLL Lowpass Filter
When the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple
and reliable method for limiting current. The resistor may also prevent damage in the case of a
power failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
VCCPLL Pin Requirements
To reduce clock skew on the 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL)
circuit is isolated on the pinout. The lowpass filter, as shown in
clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be
low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node connecting
VCCPLL must be as short as possible.
When the voltage on the VCCPLL power supply pin exceeds the V
time, including the power up and power down sequences, excessive currents may permanently
damage on-chip electrostatic discharge (ESD) protection diodes. The damage may accumulate over
multiple episodes.
In actual applications, this problem occurs only when the VCCPLL and V
separate power supplies or voltage regulators. Applications that use one power supply for
VCCPLL and V
VCCPLL voltage to exceed V
The VCCPLL low-pass filter recommendation does not promote this problem.
Symbol
VDIFF
(Board Plane)
V
CC
Parameter
VCC5-V
Difference
CC
CC
are not typically at risk. Verify that your application does not allow the
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Min
100
10
CC
(80960JS/JC/JT)
(80960JA/JF/JD)
by 0.5 V.
Max
2.25
Units
V
+
4.7 µF
VCC5 input should not exceed V
during power-up and power-down, or during steady-
state operation.
0.01 µF
Figure
CC
Notes
pin voltage by 0.5 V at any
9, reduces noise induced
CC
CC
(On 80960Jx)
pins are driven by
VCCPLL
by more than 2.25 V
F_CA078A
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