MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 149

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

dler is enabled. If the destination is a floating-point data register, the register is not affected,
and a pre-instruction exception is reported. If the destination is a memory or integer data
register, then an undefined result is stored, and a post-instruction exception is taken imme-
diately. In addition, the processor incorrectly reports an underflow exception if the result of
a floating-point multiply is a normalized number with an exponent of $0000. Exception pro-
cessing begins with the M68060SP UNFL exception handler to provide MC68881-compati-
ble operation. The M68060SP then determines whether or not control is passed back to
normal instruction flow (the OVFL bit in the FPCR exception enable byte is cleared), to the
user OVFL handler (the OVFL bit in the FPCR exception enable byte is set) or the user INEX
handler (the OVFL bit in the FPCR exception enable byte is cleared, but the INEX bit in the
FPCR exception enable byte is set and the corresponding INEX bit in the FPSR EXC byte
is also set).
6.6.5.1 TRAP DISABLED RESULTS (FPCR UNFL BIT CLEARED). The result that is
stored in the destination is either a denormalized number or zero. Denormalization is accom-
plished by shifting the mantissa of the intermediate result to the right while incrementing the
exponent until it is equal to the denormalized exponent value for the destination format. The
denormalized intermediate result is rounded to the selected rounding precision or destina-
tion format.
If, in the process of denormalizing the intermediate result, all of the significant bits are shifted
off to the right, the selected rounding mode determines the value to be stored at the desti-
nation, as shown in Table 6-14.
6.6.5.2 TRAP ENABLED RESULTS (FPCR UNFL BIT SET). The result stored in the des-
tination is the same as the result stored when traps are disabled. For an FMOVE OUT, the
operand is stored in the destination memory or integer data register before control is passed
to the user UNFL handler as a post-instruction exception. Otherwise, if the destination is a
floating-point data register, control is passed to the user UNFL handler as a pre-instruction
exception when the next floating-point instruction is encountered.
MOTOROLA
Rounding Mode
RN
RM
RZ
RP
Table 6-14. Underflow Rounding Mode Values
Zero, with the sign of the intermediate result.
Zero, with the sign of the intermediate result.
For positive overflow, + zero; for negative underflow, smallest denormalized neg-
ative number.
For positive overflow, smallest denormalized positive number; for negative under-
flow, –zero.
M68060 USER’S MANUAL
Result
Floating-Point Unit
6-31