MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 194

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

retry termination simply retries the LPSTOP broadcast cycle. The lower data bits D15–D0
are driven with the LPSTOP immediate word value and the upper data bits D31–D16 are
driven high. After a number of CLK cycles, PSTx change to $16. The timing of when the
PSTx signals are updated relative to the LPSTOP broadcast cycle is undefined.
Once the LPSTOP broadcast cycle is finished, no bus arbitration activity is performed by the
MC68060. Furthermore, it is imperative that no alternate master bus activity be done from
the time the LPSTOP broadcast cycle is finished to when the LPSTOP encoding is indicated
by PSTx. For systems that require the MC68060 to be three-stated when in the LPSTOP
mode, the bus must be arbitrated away during the LPSTOP broadcast cycle. This is easily
achieved by having the BG input negated at the same time as TA or TEA. For additional
power savings, CLK may be stopped in the low state while in the LPSTOP mode. Systems
must ensure that CLK only be stopped when the PSTx signals indicate $16.
Figure 7-32 illustrates a flowchart of the LPSTOP broadcast cycle. Figure 7-33 and Figure
7-34 illustrate functional timing diagrams for an LPSTOP broadcast cycle as a function of
BG.
MOTOROLA
10) DRIVE SIZ1–SIZ0 TO BYTE
11) ASSERT TS FOR ONE BCLK
12) ASSERT TIP
13) ASSERT SAS IMMEDIATELY IF
Figure 7-30. Breakpoint Interrupt Acknowledge Cycle Flowchart
1) IF NORMAL OR BUS ERROR TERMINATION
2) IF RETRY TERMINATION, RETRY BREAK-
1) SET R/W TO READ
3) DRIVE ADDRESS ON A31–A0 TO $00000000
4) DRIVE UPA1–UPA0 = 0
5) DRIVE TT1–TT0 = 3
6) DRIVE TM2–TM0 = 0
7) DRIVE TLN1–TLN0 = 0
8) ASSERT BS0
9) NEGATIVE CIOUT, LOCK, LOCKE, BS3–BS1
1) NEGATE TIP OR START NEXT CYCLE
2) INITIATE EXCEPTION PROCESSING
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER READ PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
TAKE EXCEPTION USING VECTOR 4
(ILLEGAL INSTRUCTION EXCEPTION
VECTOR) AFTER COMPLETION OF BUS
CYCLE
POINT ACKNOWLEDGE CYCLE
PROCESSOR
M68060 USER’S MANUAL
1) DECODE ADDRESS AND ATTRIBUTES
2) ASSERT TA, TEA, OR TRA FOR ONE BCLK
SYSTEM
Bus Operation
7-39