MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 328

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications Information
I/O devices that normally incur bus errors need to be aware that the MC68060 has an impre-
cise exception mode that may need to be addressed.
11.1.3 Precise Vs. Imprecise Exception Mode
Systems that do not rely on the bus error (TEA asserted) in normal operation are not
affected much by the differences between the precise and imprecise exception mode.
The MC68060 provides the precise and imprecise exception modes to allow system soft-
ware to assign the severity of bus errors (TEA asserted) on write cycles. In general, bus
errors on writes are recoverable in the precise exception mode, but not in the imprecise
exception mode. The MC68040 provides a precise exception mode, but at the expense of
performance and a large access error stack frame.
For systems that require precise bus error write cycles in a normal operating environment,
it is possible to disable the store buffer via the MOVEC of CACR instruction. This impacts
performance significantly, and must be carefully considered before doing so. Also, note that
even with the store buffers disabled, a bus error caused by a push buffer write is still nonre-
coverable.
11.1.4 Other Considerations
The following is a list of other concerns that are unlikely to affect system software, but are
included for completeness.
11.2 USING AN MC68060 IN AN EXISTING MC68040 SYSTEM
This document outlines the issues involved in using an MC68060 in an existing MC68040
socket. It is assumed that for these applications, the MC68060 is made to operate in the half-
speed bus mode.
11.2.1 Power Considerations
The MC68060 operates at a supply voltage of 3.3 V, not 5 V. The MC68060 interfaces glue-
lessly to transistor-transistor logic (TTL) levels.The following paragraphs discuss the two
main issues of the lower, 3.3-V supply voltage.
11.2.1.1 DC TO DC VOLTAGE CONVERSION. The first issue involves the DC-to-DC volt-
age conversion for the MC68060 V
to this problem.
11-6
1. Some of the exception priorities for multiple exceptions on the MC68060 are different
2. Unlike the MC68040, the MC68060 provides only one snoop control signal, the snoop
than the MC68040 (see Section 8 Exception Processing for priority groupings). This
shouldn’t affect the way interrupts are handled, an interrupt is the lowest priority excep-
tion on both microprocessors.
invalidate signal (SNOOP). System software may need to CPUSH the cache before
DMA activity is initiated. Alternatively, the cache mode may be changed to write-
through cacheable for all shared memory areas.
M68060 USER’S MANUAL
dd
pins. The following paragraphs discuss two solutions
MOTOROLA