MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 61

IC MPU 32BIT 50MHZ 206-PGA

MC68EC060RC50

Manufacturer Part Number
MC68EC060RC50
Description
IC MPU 32BIT 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68EC060RC50

Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC060RC50
Manufacturer:
NXP
Quantity:
1 746
2.10.2 MC68060 Processor Clock (CLK)
CLK is the synchronous clock of the MC68060. This signal is used internally to clock or
sequence the internal logic of the MC68060 processor and is qualified with CLKEN to clock
all external bus signals.
Since the MC68060 is designed for static operation, CLK can be gated off to lower power
dissipation (e.g., during low-power stopped states). Refer to Section 7 Bus Operation for
more information on low-power stopped states.
2.10.3 Clock Enable (CLKEN)
This input signal is a qualifier for the MC68060 processor clock (CLK) and is provided to sup-
port lower bus frequency MC68060 designs. The internal MC68060 bus interface controller
will sample, assert, negate, or three-state signals (except for BB and TIP which can three-
MOTOROLA
Hex
$0C
$0D
$1C
$1D
$0A
$0B
$0E
$0F
$1A
$1B
$1E
$1F
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
PST4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PST3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PST2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PST1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 2-7. PSTx Encoding
M68060 USER’S MANUAL
PST0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Continue Execution in User Mode
Complete 1 Instruction in User Mode
Complete 2 Instructions in User Mode
Emulator Mode Entry Exception Processing
Complete Not Taken Branch in User Mode
Complete Not Taken Branch Plus 1 Instruction in User Mode
IED Cycle of Branch to Vector, Emulator Entry Exception
Complete Taken Branch in User Mode
Complete Taken Branch Plus 1 Instruction in User Mode
Complete Taken Branch Plus 2 Instructions in User Mode
Continue Execution in Supervisor Mode
Complete 1 Instruction in Supervisor Mode
Complete 2 Instructions in Supervisor Mode
Complete RTE Instruction in Supervisor Mode
Low-Power Stopped State; Waiting for an Interrupt or Reset
MC68060 Is Stopped Waiting for an Interrupt
MC68060 Is Processing an Exception
Complete Not Taken Branch in Supervisor Mode
Complete Not Taken Branch Plus 1 Instruction in Supervisor Mode
IED Cycle of Branch to Vector, Exception Processing
MC68060 Is Halted
Complete Taken Branch in Supervisor Mode
Complete Taken Branch Plus 1 Instruction in Supervisor Mode
Complete Taken Branch Plus 2 Instructions in Supervisor Mode
Internal Processor Status
Signal Description
2-15

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