MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 256

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Exception Processing
PF—Page Fault
SP—Supervisor Protect
WP—Write Protect
TWE—Bus Error (TEA asserted) on Table Search
RE—Bus Error (TEA asserted) on Read
WE—Bus Error (TEA asserted) on Write
TTR—TTR Hit
BPE—Branch Prediction Error
SEE—Software Emulation Error
8-24
Refer to 8.4.7 Branch Prediction Error for details on this error type.
The processor does not set the SEE bit. This bit is used by the M68060SP to indicate a
software emulation error case. Refer to Appendix C MC68060 Software Package for
details on how this bit is set.
0 =Fault not due to an invalid page descriptor.
1 =Fault due to an invalid page descriptor.
0 =Fault not due to user process accessing a page that is supervisor protected.
1 =Fault due to user process accessing a page that is supervisor protected.
0 =Fault not due to a write access on a write-protected page.
1 =Fault due to a write access on a write-protected page.
0 =Fault is not caused by a bus error during any MMU table search read or write.
1 =Fault is caused by a bus error during any MMU table search read or write.
0 =Fault is not caused by a bus error on a read cycle.
1 =Fault is caused by a bus error on a read cycle.
0 =Fault is not caused by a bus error on a write cycle.
1 =Fault is caused by a bus error on a write cycle.
0 =Fault is detected on an access that is mapped by the a paged MMU translation or a
1 =Fault is detected on an access that is mapped by one of the four TTRs.
0 =Fault is not caused by a branch prediction error.
1 =Fault is caused by a branch prediction error.
0 =Fault is not caused by a software emulation error.
1 =Fault is caused by a software emulation error.
default TTR translation.
M68060 USER’S MANUAL
MOTOROLA