MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 109

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

In Table 7-5, the following notation applies:
7.4 IMMEDIATE INSTRUCTION EXECUTION TIMES
The numbers of clock periods shown in Table 7-6 include the times to fetch immediate
operands, perform the operations, store the results, and read the next operation. The total
number of clock periods, the number of read cycles, and the number of write cycles are
7-4
An — Address register operand
Dn — Data register operand
ea — An operand specified by an effective address
M
— Memory effective address operand
ADD/ADDA
AND
CMP/CMPA
DIVS
DIVU
EOR
MULS
MULU
OR
SUB
MULS, MULU — The multiply algorithm requires 42+2n clocks where n is defined as:
DIVS, DIVU — The divide algorithm used by the MC68008 provides less than 10% difference
*** Only available effective address mode is data register direct.
Instruction
** The base time of 10 clock periods is increased to 12 if the effective address mode is
+ Add effective address calculation time.
* Indicates maximum base value added to word effective address time
register direct or immediate (effective address time should also be added).
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Table 7-5. Standard Instruction Execution Times
between the best- and worst-case timings.
MULS: n = tag the <ea> with a zero as the MSB; n is the resultant number of 10
or 01 patterns in the 17-bit source; i.e., worst case happens when the source
is $5555.
MULU: n = the number of ones in the <ea>
Freescale Semiconductor, Inc.
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op<ea>, An
10(2/0)+**
10(2/0)+**
12(2/0)+
10(2/0)+
10(2/0)+
12(2/0)+
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op<ea>, Dn
12(2/0)+***
10(2/0)+**
10(2/0)+**
162(2/0)+*
144(2/0)+*
10(2/0)+**
10(2/0)+**
8(2/0)+***
8(2/0)+***
74(2/0)+*
74(2/0)+*
10(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
8(2/0)+
op Dn, <M>
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
12(2/1)+
16(2/2)+
24(2/4)+
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