MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 23

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Notation for operands:
Notation for subfields and qualifiers:
Notations for operations that have two operands, written <operand> <op> <operand>,
where <op> is one of the following:
MOTOROLA
–(<address register>) — Indicates that the operand register points to the memory
(<address register>)+ — Location of the instruction operand—the optional mode
(<address register>) — The register indirect operator
<bit> of <operand> — Selects a single bit of the operand
<ea>{offset:width} — Selects a bit field
#xxx or #<data> — Immediate data that follows the instruction word(s)
Immediate Data — Immediate data from the instruction
<operand>10 — The operand is binary-coded decimal, operations are
(<operand>) — The contents of the referenced location
Destination — Destination contents
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
Source — Source contents
Vector — Location of exception vector
<fmt> — Operand data format: byte (B), word (W), long (L), single
FPm — One of eight floating-point data registers (always
FPn — One of eight floating-point data registers (always
Freescale Semiconductor, Inc.
+inf — Positive infinity
–inf — Negative infinity
PC — Program counter
SR — Status register
For More Information On This Product,
V — Overflow condition code
V — Logical OR
+ — The operands are added
– — The destination operand is subtracted from the source
< — Relational test, true if source operand is less than
> — Relational test, true if source operand is greater than
— The source operand is moved to the destination operand
— The two operands are exchanged
— The operands are multiplied
— The source operand is divided by the destination
— Logical exclusive OR
— Logical AND
(S), double (D), extended (X), or packed (P).
specifies the source register)
specifies the destination register)
performed in decimal
qualifiers are –, +, (d), and (d, ix)
operand
operand
destination operand
destination operand
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