MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 76

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

executing a reset instruction is ignored. Since the processor asserts the RESET signal for
124 clock cycles during execution of a reset instruction, an external reset should assert
RESET for at least 132 clock periods.
5.6 THE RELATIONSHIP OF
To properly control termination of a bus cycle for a retry or a bus error condition, DTACK,
BERR, and HALT should be asserted and negated on the rising edge of the processor
clock. This relationship assures that when two signals are asserted simultaneously, the
required setup time (specification #47, Section 9 Electrical Characteristics) for both of
them is met during the same bus state. External circuitry should be designed to
incorporate this precaution. A related specification, #48, can be ignored when DTACK,
BERR, and HALT are asserted and negated on the rising edge of the processor clock.
The possible bus cycle termination can be summarized as follows (case numbers refer to
Table 5-5).
Normal Termination:
Halt Termination:
Bus Error Termination:
Retry Termination:
Table 5-1 shows the details of the resulting bus cycle termination in the M68000
microprocessors for various combinations of signal sequences.
5-30
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
DTACK is asserted. BERR and HALT remain negated (case 1).
HALT is asserted coincident with or preceding DTACK, and
BERR remains negated (case 2).
BERR is asserted in lieu of, coincident with, or preceding
DTACK (case 3). In the MC68010, the late bus error also,
BERR is asserted following DTACK (case 4). HALT remains
negated and BERR is negated coincident with or after DTACK.
HALT and BERR asserted in lieu of, coincident with, or before
DTACK (case 5). In the MC68010, the late retry also, BERR
and HALT are asserted following DTACK (case 6). BERR is
negated coincident with or after DTACK. HALT must be held at
least one cycle after BERR.
Go to: www.freescale.com
DTACK
,
BERR
, AND
HALT
MOTOROLA