IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 

Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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APPLICATIONS INFORMATION
SWITCHING REGULATOR OVERVIEW
The LTC4269-1 includes a current mode converter designed
specifi cally for use in an isolated fl yback topology employing
synchronous rectifi cation. The LTC4269-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an opto-isolator in isolated designs,
thus greatly improving dynamic response and reliability.
The LTC4269-1 has a unique feedback amplifi er that
samples a transformer winding voltage during the fl yback
period and uses that voltage to control output voltage.
The internal blocks are similar to many current mode
controllers. The differences lie in the feedback amplifi er and
load compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
fl yback control. For more information on the basics of
current mode switcher/controllers and isolated fl yback
converters see Application Note 19.
Feedback Amplifi er—Pseudo DC Theory
For the following discussion, refer to the simplifi ed
Switching Regulator Feedback Amplifi er diagram (Figure
10A). When the primary-side MOSFET switch MP turns off,
its drain voltage rises above the V
PORTP
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During fl yback the voltage on
nondriven transformer pins is determined by the secondary
voltage. The amplitude of this fl yback pulse, as seen on
the third winding, is given as:
(
+I
• ESR + R
V
OUT
SEC
DS(ON)
=
V
FLBK
N
SF
R
= on-resistance of the synchronous MOSFET MS
DS(ON)
I
= transformer secondary current
SEC
ESR = impedance of secondary circuit capacitor, winding
and traces
N
= transformer effective secondary-to-fl yback winding
SF
turns ratio (i.e., N
/N
)
S
FLBK
The fl yback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifi er compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifi er whose output is connected to V
a period in the fl yback time. An external capacitor on
the V
pin integrates the net feedback amp current to
CMP
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V
the overall loop. The relationship between V
is expressed as:
R1+ R2
=
V
FLBK
Combining this with the previous V
an expression for V
programming resistors and secondary resistances:
=
V
⎝ ⎜
OUT
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory). The practical aspects of applying this equation for
V
are found in subsequent sections of the Applications
OUT
Information.
Feedback Amplifi er Dynamic Theory
rail. Flyback occurs
So far, this has been a pseudo-DC treatment of fl yback
feedback amplifi er operation. But the fl yback signal is a
pulse, not a DC level. Provision is made to turn on the
fl yback amplifi er only when the fl yback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
)
Minimum Output Switch On Time (t
The LTC4269-1 affects output voltage regulation via
fl yback pulse action. If the output switch is not turned on,
there is no fl yback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for t
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
LTC4269-1
only during
CMP
because of the high gain in
FB
FLBK
• V
FB
R2
expression yields
FLBK
in terms of the internal reference,
OUT
(
R1+ R2
−I
• ESR + R
• V
• N
⎠ ⎟
FB
SF
SEC
DS(ON)
R2
)
ON(MIN)
. If the output load
ON(MIN)
and V
FB
)
42691fb
21