IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 


Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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LTC4269-1
APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
between the primary-side switch and secondary-side syn-
chronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
( )
+ 47
t
ns
( )
PGDLY
=
R
PGDLY
9.01
A good starting point is 15k.
Soft-Start Function
The LTC4269-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
pin from exceeding that on the SFST
CMP
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when V
is too low (undervoltage lockout),
CC
current sense voltage is greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
node voltage is also pulled low
CMP
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
C
• 1.4V
SFST
=
= 70kΩ • C
t
SS
SFST
20µA
30
Switcher’s UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at V
equal to the change in bias current times R
procedure is to select the desired V
hysteresis, V
V
UVHYS
=
R
A
I
UVLO
where:
I
= I
UVLO
UVLOL
R
is then selected with the desired turn-on voltage:
B
=
R
B
V
IN(ON)
⎝ ⎜
V
UVLO
I
UVLO
( )
µF
V
IN
R
A
UVLO
LTC4969-1
R
B
(13a) UV Turning On
Figure 13. UVLO Pin Function and Recommended Filtering
. The gate drivers are disabled when
IN
. The design
A
referred voltage
IN
. Then:
UVHYS
– I
is approximately 3.4μA
UVLOH
R
A
– 1
⎠ ⎟
I
UVLO
V
IN
R
A
C
UVLO
UVLO
LTC4969-1
R
B
(13b) UV Turning Off
(13c) UV Filtering
is
IN
V
IN
R
A1
R
A2
UVLO
R
B
42691 F13
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