IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 106

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

Table 41: Various Operation Modes in Receive Path for Reference (Continued)
IDT82V2108
Table 42: Various Operation Modes in Transmit Path for Reference
Operation
Note:
1. In the ‘Register’ column, except for the Receive Multiplexed mode, the register position of the Framer 1 is listed to represent the set of the registers of eight framers. The other registers
positions are tabulated in ‘Register Map’. However, in Receive Multiplexed mode, the register positions of eight framers are all listed.
2. The ‘Description’ illustrates the fundamental function of the operation mode. The others can be configured as desired.
Signaling Mode
Transmit Clock
Transmit Clock
Slave External
Receive Multi-
Enable Mode
plexed Mode
Slave TSFS
(Continued)
Mode
Mode
Register
Register
018H
003H
040H
004H
027H
018H
003H
040H
004H
027H
091H
191H
291H
391H
012H
092H
192H
212H
292H
312H
392H
013H
093H
193H
213H
293H
313H
393H
011H
111H
211H
311H
112H
113H
1
1
Value (from Bit7 to Bit0)
Value (from Bit7 to Bit0)
00100001
01000000
00010000
00100001
00000000
00010000
01110000
01110000
00001111
00001111
00100000
00100000
00100000
00100000
00100000
00100000
00100000
00100000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000000
00000001
00000010
00000000
00000001
00000010
00000011
00000011
In the Transmit Clock Slave mode. The FE is logic 0 and the DE is logic 0.
In the Transmit Clock Slave External Signaling mode.
Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated.
TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
The FIFO is set to self-center its read pointer.
In the Transmit Clock Slave mode. The FE is logic 0 and the DE is logic 0.
In the Transmit Clock Slave TSFS Enable mode.
Channel Associated Signaling (CAS) is enabled. The CRC Multi-Frame is generated.
TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
The FIFO is set to self-center its read pointer.
The MRSCFS is used.
Enable the normal operation of the MRSD and MRSSIG pins.
TSOFF[6:0] = 0. The time slot offset is 0.
TSOFF[6:0] = 1. The time slot offset is 1.
TSOFF[6:0] = 2. The time slot offset is 2.
TSOFF[6:0] = 3. The time slot offset is 3.
TSOFF[6:0] = 0. The time slot offset is 0.
TSOFF[6:0] = 1. The time slot offset is 1.
TSOFF[6:0] = 2. The time slot offset is 2.
TSOFF[6:0] = 3. The time slot offset is 3.
96
Description
Description
2
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009