IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 152

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Receive Path Frame Pulse Configuration (00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH)
PERTS_RSFS, REF_MRSFS:
OOCMFE0:
dure in Annex B of G.706).
G706RAI:
chooses one of two criteria to define the conditions. If the AUTOYELLOW (b3, E1-00H) is ‘0’, G706RAI does not have any effect.
when the off-line searching indicates out of Basic frame. This definition follows the ETSI standards.
declared nor when offline out-of frame is declared. This definition follows the Annex B of G.706.
E1 Receive Backplane Configuration (010H, 090H, 110H, 190H, 210H, 290H, 310H, 390H)
FRACTN[1:0]:
lowing table. The two bits will be ignored if the Receive Clock Slave mode is enabled (RSCKSLV = 1, b5, E1-010H).
Programming Information
PERTS_RSFS
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
In Receive Multiplexed mode, these two bits in the eight framers should be set to the same value.
This bit chooses one of two operation modes concerning the transmission of E-bits when the framer is out of CRC-4 multiframe.
= 0: Transmit ‘One’s for the E-bits while out of CRC-4 Multi-Frame.
= 1: Transmit ‘Zero’s for the E-bits while out of CRC-4 Multi-Frame. (This setting is compliant with the CRC-4 to non-CRC-4 interworking proce-
When the AUTOYELLOW (b3, E1-00H) is set as ‘1’, which means the RAI bit will be transmitted automatically in certain conditions, this bit
= 0: The RAI bit will be transmitted when out of Basic Frame, when AISD is declared, when CRC-4 to non-CRC-4 interworking is declared or
= 1: The RAI bit will be transmitted when out of Basic frame or when AISD is declared, but not when CRC-4 to non-CRC-4 interworking is
When Receive Clock Master mode is enabled (RSCKSLV = 0, b5, E1-010H), these two bits selects one of the operation modes shown in the fol-
X
0
1
FRACTN[1]
REF_MRSFS
R/W
7
7
0
0
0
1
The pulse output on the RSFS/MRSFS pin is forced to be logic 0.
The signal on the RSFS/MRSFS pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP (b3b2b1b0, E1-011 H).
RSFSn/MRSFS contains a reference frame pulse identical to the receive system side common frame pulse on the RSCFS/
MRSCFS pin.
FRACTN[0]
R/W
6
6
0
FRACTN[1:0]
0 0
0 1
1 0
1 1
Reserved
RSCKSLV
R/W
5
5
1
Receive Clock Master Fractional E1 with F-bit mode
Receive Clock Master Fractional E1 mode
R/W
DE
Receive Clock Master Full E1 mode
4
4
1
142
Pulse on the RSFSn/MRSFS
Operation Mode
PERTS_RSFS
Reserved
R/W
R/W
FE
3
0
3
1
REF_MRSFS
CMS
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
OOCMFE0
RATE[1]
R/W
R/W
1
0
1
0
March 5, 2009
G706RAI
RATE[0]
R/W
R/W
0
0
0
0