IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 269

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 TBOM Code (05DH, 0DDH, 15DH, 1DDH, 25DH, 2DDH, 35DH, 3DDH)
writing any HDLC packets currently being transmitted. The BOM pattern is ‘111111110BOC[0]BOC[1]BOC[2]BOC[3]BOC[4]BOC[5]0’, that is, the
BOC[0] is transmitted first.
T1 / J1 PRGD Control (060H)
PDR[1:0]:
PS:
TINV:
RINV:
AUTOSYNC:
MANSYNC:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
When the BOC[5:0] are written with any 6-bit code other than the ‘111111’, the code will be transmitted as the Bit Oriented Message (BOM), over-
The PDR[1:0] define the function of the four PRGD Pattern Detector registers:
= 0: A pseudo-random pattern is generated/detected by the PRGD.
= 1: A repetitive pattern is generated/detected by the PRGD.
This bit should be set first of all the PRGD registers.
= 0: Disable inverting the generated pattern before being transmitted.
= 1: Enable inverting the generated pattern before being transmitted.
= 0: Disable inverting the received pattern before being processed.
= 1: Enable inverting the received pattern before being processed.
= 0: Disable automatic re-search for the synchronization of the pattern after the pattern is out of synchronization.
= 1: Enable automatic re-search for the synchronization of the pattern after the pattern is out of synchronization.
Trigger on the rising edge. A transition from logic 0 to logic 1 on this bit manually initiates a re-search for the synchronization of a pattern.
(The #1 is the LSB, while the #4 is the MSB.)
PDR[1]
R/W
7
7
0
Reserved
PDR[1:0]
0 0, 0 1
1 0
1 1
PDR[0]
R/W
6
6
0
Reserved
BOC[5]
R/W
5
1
5
BOC[4]
R/W
R/W
PS
4
1
4
0
PRGD Pattern Detector Registers (#1 ~ #4)
259
Pattern Receive
BOC[3]
TINV
R/W
R/W
Error Count
Bit Count
3
1
3
0
BOC[2]
RINV
R/W
R/W
2
1
2
0
T1 / E1 / J1 OCTAL FRAMER
AUTOSYNC
BOC[1]
R/W
R/W
1
1
1
1
March 5, 2009
MANSYNC
BOC[0]
R/W
R/W
0
1
0
0