IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 194

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 THDLC #1, #2, #3 Upper Transmit Threshold (051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H)
E1-00AH).
UTHR[6:0]:
The transmission will not stop until the complete packet is transmitted and the THDLC FIFO fill level is below ‘UTHR[6:0] + 1’.
E1 THDLC #1, #2, #3 Lower Interrupt Threshold (052H, 0D2H, 152H, 1D2H, 252H, 2D2H, 352H, 3D2H)
E1-00AH).
LINT[6:0]:
will be generated. The LINT[6:0] should be less than the value of the UTHR[6:0] unless both are equal to 00H.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4,
These bits define the upper fill level of the FIFO. Once the fill level exceeds the UTHR[6:0] value, the data stored in the FIFO will start to transmit.
Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4,
These bits define the fill level of the FIFO that can introduce an interrupt. That is, when the fill level of the FIFO is below the LINT[6:0], an interrupt
It should be greater than the value of the LINT[6:0] unless both are equal to 00H.
Reserved
Reserved
7
7
UTHR[6]
LINT[6]
R/W
R/W
6
1
6
0
UTHR[5]
LINT[5]
R/W
R/W
5
0
5
0
UTHR[4]
LINT[4]
R/W
R/W
4
0
4
0
184
UTHR[3]
LINT[3]
R/W
R/W
3
0
3
0
UTHR[2]
LINT[2]
R/W
R/W
2
0
2
1
T1 / E1 / J1 OCTAL FRAMER
UTHR[1]
LINT[1]
R/W
R/W
1
0
1
1
March 5, 2009
UTHR[0]
LINT[0]
R/W
R/W
0
0
0
1