IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 243

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 TPLC µP Access Status (031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H)
BUSY:
more operations to the indirect registers could be done until this bit is cleared.
T1 / J1 TPLC Channel Indirect Address / Control (032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H)
R/WB:
A[6:0]:
T1 / J1 TPLC Channel Indirect Data Buffer (033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H)
isters, the byte to be written must be written into this register before the target indirect register address and R/WB = 0 is written into the Address/Con-
trol register, initiating the access. If data is to be read from the indirect registers, only the target indirect register address and R/WB = 1 is written into
the Address/Control register, initiating the request. After 490 ns, this register will contain the requested data byte.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Bit No.
Default
Bit No.
Bit No.
Type
Type
= 0: No reading or writing operation on the indirect registers.
= 1: An internal indirect register is being accessed, any new operation on the internal indirect register is not allowed.
This bit goes low timed to an internal high-speed clock rising edge after the operation has been completed. The operation cycle is 650 ns. No
Writing to this register with a valid address and Read/Write command initiates an internal operation cycle to the indirect registers.
= 0: Write the data to the specified indirect register.
= 1: Read the data from the specified indirect register.
Specify the address of the indirect registers (from 01H to 48H) for the microprocessor access.
This register holds the value which will be read from or write into the indirect registers (from 01H to 48H). If data is to be written to the indirect reg-
Type
BUSY
R/WB
R/W
R/W
D7
R
7
0
7
0
7
0
R/W
R/W
A6
D6
6
0
6
6
0
R/W
R/W
A5
D5
5
0
5
5
0
R/W
R/W
A4
D4
4
4
0
4
0
233
Reserved
R/W
R/W
D3
A3
3
0
3
0
3
R/W
R/W
D2
A2
2
0
2
0
2
T1 / E1 / J1 OCTAL FRAMER
R/W
R/W
D1
A1
1
0
1
1
0
March 5, 2009
R/W
R/W
D0
A0
0
0
0
0
0