IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 158

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Transmit Backplane Frame Pulse Configuration (019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H)
FPINV:
FPTYP:
each CRC Multi-Frame.
E1 Transmit Backplane Parity Configuration and Status (01AH, 09AH, 11AH, 19AH, 21AH, 29AH, 31AH, 39AH)
TPTYP:
the position when the number of ‘One’s in the previous Basic Frame is odd.
position when the number of ‘One’s in the previous Basic Frame is even.
TPTYE:
TDI:
PTY_EXTD:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
= 0: The positive pulse on the TSCFS pin is valid.
= 1: The negative pulse on the TSCFS pin is valid.
The FPINV of the eight framers should be the same value.
= 0: Indicate that the signal on the TSCFS pin pulses during the first bit of each Basic Frame.
= 1: Indicate that the signal on the TSCFS pin asserts on the first bit of each Signaling Multi-Frame and asserts oppositely following the first bit of
The FPTYP of the eight framers should be the same value.
= 0: Even parity is employed in the first bit of TS0 of each Basic Frame input from the TSDn/MTSD pin, which means a logic one is expected in
= 1: Odd parity is employed in the first bit of TS0 of each Basic Frame input from the TSDn/MTSD pin, which means a logic one is expected in the
This bit decides whether to generate an interrupt when a parity error is detected on the TSDn/MTSD pin.
= 0: No interrupt is generated when a parity error is detected on the TSDn/MTSD pin.
= 1: An interrupt on the INT pin is generated when a parity error is detected on the TSDn/MTSD pin.
This bit indicates the parity error detected on the TSDn/MTSD pin.
= 0: No parity error is detected on the TSDn/MTSD pin.
= 1: A parity error is detected on the TSDn/MTSD pin.
This bit is cleared to ‘0’ when it is read.
= 0: The parity checking is calculated over the previous Basic frame, excluding the first bit of TS0 on the TSDn/MTSD pin.
= 1: The parity checking is calculated over the previous Basic frame, including the first bit of TS0 on the TSDn/MTSD pin.
TPTYP
R/W
7
7
0
TPTYE
R/W
6
6
0
Reserved
TDI
R
X
5
5
Reserved
4
4
148
PTY_EXTD
FPINV
R/W
R/W
3
0
3
0
Reserved
2
2
T1 / E1 / J1 OCTAL FRAMER
Reserved
FPTYP
R/W
1
0
1
March 5, 2009
Reserved
0
0