IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 216

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 PRGD Pattern Detector #1 (07CH)
E1 PRGD Pattern Detector #2 (07DH)
E1 PRGD Pattern Detector #3 (07EH)
E1 PRGD Pattern Detector #4 (07FH)
They reflect the content of the received pattern.
value in these registers represents the number of the bit errors. The bit errors are not accumulated when the pattern is out of synchronization.
in these registers represents the total received bit number.
of these four registers, or to the Revision / Chip ID / Global PMON register.
Programming Information
Bit Name
Bit Name
Bit Name
Bit Name
Default
Default
Bit No.
Default
Bit No.
Bit No.
Default
Bit No.
Type
Type
When the PDR[1:0] (b7~6, E1-070H) are set to ‘00’ or ‘01’, the four PRGD pattern detector registers are configured as Pattern Receive registers.
When the PDR[1:0] (b7~6, E1-070H) are set to ‘10’, the four PRGD pattern detector registers are configured as Error Counter registers. The
When the PDR[1:0] (b7~6, E1-070H) are set to ‘11’, the four PRGD pattern detector registers are configured as Bit Counter registers. The value
These registers can be configured to update every second automatically when the AUTOUPDATE (b0, E1-000H) is set to ‘1’, or by writing to any
Type
Type
PD[15]
PD[31]
PD[23]
PD[7]
R
X
R
X
7
7
R
X
7
R
X
7
PD[14]
PD[30]
PD[22]
PD[6]
R
R
6
X
6
X
R
X
6
R
X
6
PD[13]
PD[29]
PD[21]
PD[5]
R
X
R
X
5
5
R
X
5
R
5
X
PD[12]
PD[28]
PD[20]
PD[4]
R
X
R
X
4
R
X
4
4
206
R
4
X
PD[19]
PD[27]
PD[11]
PD[3]
R
X
R
X
R
X
3
3
3
R
X
3
PD[18]
PD[26]
PD[10]
PD[2]
R
X
R
2
R
R
X
2
X
2
X
2
T1 / E1 / J1 OCTAL FRAMER
PD[17]
PD[25]
PD[1]
PD[9]
R
X
R
X
1
1
R
X
R
X
1
1
March 5, 2009
PD[16]
PD[24]
PD[0]
PD[8]
R
X
R
X
0
0
R
X
R
X
0
0