SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet

Page 1

Swissbit AG Swissbit reserves the right to change products or specifications without notice. Industriestrasse 4 CH-9552 Bronschhofen Switzerland Product data sheet Parallel ATA (PATA) 2.5”-Solid State Drive P-120 Series up to UDMA4 / MDMA2 / PIO4 Standard and industrial temperature ...

Page 2

Parallel ATA (PATA) 2.5-inch Solid State Drive (SSD 32GByte, 5V (or 3.3V) supply 1 Feature summary 2.5-inch ATA Solid State Drive (SSD) 100.2mm x 70.0mm x 9.0mm o Replacement of a standard IDE/ATA-compliant Hard Disk Drive (HDD) Highly-integrated ...

Page 3

Contents 1 FEATURE SUMMARY ..................................................................................................................................................... 2 2 CONTENTS .................................................................................................................................................................... 3 3 ORDER INFORMATION ................................................................................................................................................. 5 3.1 O OEM FFERED OPTIONS ........................................................................................................................................... 5 4 PRODUCT SPECIFICATION ............................................................................................................................................. 6 4 YSTEM ERFORMANCE ............................................................................................................................................ 6 4 NVIRONMENTAL PECIFICATIONS ...

Page 4

R (1X ) ............................................................................................................................................ 50 ECALIBRATE H 8. (03 ) ....................................................................................................................................... 51 EQUEST ENSE H 8. (F6 ECURITY ISABLE ASSWORD 8. (F3 ) ........................................................................................................................... 52 ECURITY RASE REPARE H 8.22 S ...

Page 5

Order Information Available Standard part numbers FIX / PIO4, MDMA2, UDMA4 / 0°C – 70°C Density Part Number 2GB SFPA2048QxBO2TO-C-MS-2y3-STD 4GB SFPA4096QxBO2TO-C-DT-2y3-STD SFPA8192QxBO2TO-C-QT-2y3-STD 8GB 16GB SFPA16GBQxBO4TO-C-QT-2y3-STD 32GB SFPA32GBQxBO8TO-C-QT-2y3-STD Table 1: Standard temperature product list x depends on product generation, ...

Page 6

Product Specification The Solid State Drive (SSD small form factor non-volatile memory drive which provides high capacity data storage. The drive with the IDE interface (2.00mm pitch) operates in three transfer modes: UDMA (Ultra Direct Memory Access) ...

Page 7

Environmental Specifications 4.2.1 Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Commercial Operating Temperature Industrial Operating Temperature Power Supply VCC Voltage (5V) Power Supply VCC Voltage (3.3V) Table 5: Current consumption (1) Current Consumption (type) Read (typ/max) Write ...

Page 8

Drive geometry / CHS parameter Table 10: SSD capacity specification Capacity Default_cylinders 4GB 7,732 8GB 15,880 16GB 16,383*) 32GB 16,383*) *) The CHS access is limited to about 8GB. Above 8GB the drive must be addressed in LBA mode. ...

Page 9

Electrical interface 5.1 Electrical description The SSD is connected with a standard IDE 44 pin connector (pitch 2.00mm). The power is connected at pin 41-44. The Master card can be configured as Master or slave with a jumper at ...

Page 10

Pin Signal description Type This is IORDY from the card O from the drive to the host Not used. I This is an interrupt request from the drive to the host, asking for service. This signal O is the active ...

Page 11

Electrical Specification - Table 15 Table 18 define the DC Characteristics SSD. Unless otherwise stated, conditions are: Vcc = 5V ± 10% 0°C to +70°C The current is measured by connecting an amp meter in series with the Vcc ...

Page 12

Command Interface There are two types of bus cycles and timing sequences that occur in the IDE interface, PIO and Multi-Word DMA (MDMA) as well as Ultra DMA (UDMA). Figure 1 and Figure 2 show the read and write ...

Page 13

The maximum load on –IOCS16 is 1 LSTTL with a 50pF total load the minimum total cycle time command inactive time. The actual cycle time equals the sum of the actual command inactive ...

Page 14

Ultra DMA Mode 6.3.1 Ultra DMA Overview Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the ...

Page 15

Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset. Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra ...

Page 16

Ultra DMA Data transfer phase rules 1. The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination recipient pauses an Ultra DMA burst by negating -DMARDY and resumes an ...

Page 17

Ultra DMA Data Transfers Timing Table 22 and Table 23 define the timings associated with all phases of Ultra DMA bursts. Table 22: Ultra DMA Data Burst Timing Requirements Name UDMA UDMA Mode 0 Mode 1 (ns) (ns) Min ...

Page 18

Table 23: Ultra DMA Data Burst Timing Descriptions Name Comment t Typical sustained average two cycle time 2CYCTYP t Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) CYC t Two cycle time allowing for ...

Page 19

Table 24: Ultra DMA Sender and Recipient IC Timing Requirements Name Comments t Recipient IC data setup time (from DSIC data valid until STROBE edge) (see note 2) t Recipient IC data hold time (from DHIC STROBE edge until data ...

Page 20

The device may assert DSTROBE t DSTROBE the device shall not release DSTROBE until after the host has negated -DMACK at the end of an Ultra DMA burst. k) The host shall negate STOP and assert -HDMARDY within t ...

Page 21

Sustaining an Ultra DMA Data-In Burst An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in Figure 4: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in ...

Page 22

The host shall resume an Ultra DMA burst by asserting -HDMARDY. Figure 5: Ultra DMA Data-In Burst Host Pause Timing Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP ...

Page 23

Figure 6: Ultra DMA Data-In Burst Device Termination Timing Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 6.3.2.4.5 Host Terminating an Ultra DMA Data-In Burst The ...

Page 24

If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during (9), the host shall place the result of its CRC calculation on D[15:00] (see 6.3.2 The host shall ...

Page 25

The host shall negate -CS0, -CS1, DA2, DA1, and DA0. The host shall keep -CS0, -CS1, DA2, DA1, and DA0 negated until after negating -DMACK at the end of the burst. f) Steps (c), (d), and (e) shall have ...

Page 26

The host shall drive a data word onto D[15:00]. b) The host shall generate an HSTROBE edge to latch the new word no sooner than t the state of D[15:00]. The host shall generate an HSTROBE edge no more ...

Page 27

Figure 10: Ultra DMA Data-Out Burst Device Pause Timing Notes: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after -DDMARDY is negated. 2. After negating -DDMARDY, the device may receive ...

Page 28

Figure 11: Ultra DMA Data-Out Burst Device Termination Timing Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. 6.3.2.4.10 Host Terminating an Ultra DMA Data-Out Burst Termination ...

Page 29

The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK. i) The device shall compare the CRC data received from the host with the results of its own CRC calculation miscompare ...

Page 30

The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the ...

Page 31

Figure 13: Ultra DMA Parallel CRC Generator Example Swissbit AG Swissbit reserves the right to change products or specifications without notice. Industriestrasse 4 CH-9552 Bronschhofen Switzerland www.swissbit.com industrial@swissbit.com Revision: 1.00 P-120_data_sheet_PA-QxBO_Rev100.doc Page ...

Page 32

Software interface The following section describes the hardware registers used by the host software to issue commands to the Drive. 7.1 ATA Drive Register Set Definition and Protocol The drive can be used as a high performance I/O device ...

Page 33

Bit 5 This bit is ‘0’. 7.4.4 Bit 4 (IDNF) This bit is set if the requested sector error or cannot be found. 7.4.5 Bit 3 This bit is ‘0’. 7.4.6 Bit 2 (Abort) This bit ...

Page 34

Bit 7 This bit is set to ‘1’. 7.10.2 Bit 6 (LBA) LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA ...

Page 35

Bit 5 (DWF) When set this bit indicates a Write Fault has occurred. 7.11.4 Bit 4 (DSC) This bit is set when the Drive is ready. 7.11.5 Bit 3 (DRQ) The Data Request is set when the Drive requires ...

Page 36

This read-only register is provided for compatibility with the AT disk drive interface and can be used for confirming the drive status recommended that this register is not mapped into the host’s I/O space because of potential conflicts ...

Page 37

ATA command description This section defines the software requirements and the format of the commands the Host sends to the Drive. Commands are issued to the Drive by loading the required registers in the command block with the supplied ...

Page 38

Table 34: ATA Command Set (1) Class Command 1 Check Power Mode 1 Erase Sector(s) 1 Execute Drive Diagnostic 1 Flush cache 2 Format track 1 Identify Drive 1 Idle 1 Idle Immediate 1 Initialize Drive Parameters 1 Media Lock ...

Page 39

Check Power Mode (98h or E5h) This command checks the power mode. Issuing the command while the Drive is in Standby mode, is about to enter Standby exiting Standby, the command will set BSY, set the Sector ...

Page 40

Table 38: Diagnostic Codes Code 01h 02h 03h 04h 05h 8Xh 8.4 Flush Cache (E7h) This command causes the drive to complete writing data from its cache. The drive returns status with RDY=1 and DSC=1 after the data in the ...

Page 41

Table 42: Identify Device Information Word Default Total Address Value Bytes 0 045Ah XXXXh 2 2 0000h 2 3 00XXh 2 4 0000h 2 5 0200h 2 6 XXXXh 2 7-8 XXXXh 4 9 0000h 2 10-19 aaaa ...

Page 42

Word 0: General Configuration This field indicates the general characteristics of the device. The default value for Word 0 is set to 045Ah. Some operating systems require Bit 6 of Word set to ‘1’ (Non-removable device) ...

Page 43

Word 54-56: Current Number of Cylinders, Heads, Sectors/Track These fields contain the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. 8.6.14 Word 57-58: Current Capacity This field contains the product of the current ...

Page 44

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the value in word 65. This field shall be supported by all Drives supporting DMA ...

Page 45

Words 85-87: Features/command sets enabled Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was placed in each of these words by Drives prior to ATA-4 and shall be interpreted by the host ...

Page 46

Word 93: Ultra DMA Modes Supported and Selected (if supported) Word 93 shows Hardware reset result. The contents of bits (12:0) of this word shall change only during the execution of a hardware reset. Especially Bit 13 shows cable ...

Page 47

Idle (97h or E3h) This command causes the Drive to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero interpreted as a timer count (each count is 5ms) ...

Page 48

Media Lock/Media Unlock (DEh/DFh) This command is effective an NOP command and always fails with the Drive returning command aborted. Table 46 defines the Byte sequence of the commands. Table 46: Media Lock/Media Unlock Task File Register COMMAND DRIVE/HEAD ...

Page 49

Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The amount of data transferred is indeterminate. Table 49: Read DMA Task File Register COMMAND DRIVE/HEAD CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR ...

Page 50

Table 51: Read native max address Task File Register COMMAND DRIVE/HEAD nu CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR COUNT FEATURES The LBA bit shall be set to one to specify the address is an LBA. DEV shall specify the ...

Page 51

COMMAND DRIVE/HEAD CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR COUNT FEATURES 8.19 Request Sense (03h) This command requests extended error information for the previous command. Table 55 defines the Request Sense command Byte sequence. Table 56 defines the valid extended ...

Page 52

Table 58: Security Password Data Content Word 0 Control word Bit 0: Bit 1-15: Reserved 1-16 Password (32 bytes) 17-255 Reserved 8.21 Security Erase Prepare (F3h) This command shall be issued immediately before the Security Erase Unit command to enable ...

Page 53

Table 61: Security Freeze Lock Task File Register COMMAND DRIVE/HEAD CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR COUNT FEATURES 8.24 Security Set Password (F1h) This command requests a transfer of a single sector of data from the host. Table 63 ...

Page 54

Security Unlock commands issued when the device is unlocked have no effect on the unlock counter. Table 65: Security Unlock Task File Register COMMAND DRIVE/HEAD CYLINDER HI CYLINDER ...

Page 55

Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature command is issued all data transfers shall occur on the low order D[7:0] data bus and the ...

Page 56

Feature 85h disables Advanced Power Management. Subcommand 85h may not be implemented on all devices that implement Set Features subcommand 05h. Features 0Ah and 8Ah are used to enable and disable Power Level 1 commands. Feature 0Ah is the default ...

Page 57

Using these commands outside BIOS controlled boot or shutdown may result in damage to file systems on the device. Devices should return command aborted if a subsequent non-volatile SET MAX ADDRESS command is received after a power-on or hardware reset. ...

Page 58

Table 74: S.M.A.R.T. Features Task File Register COMMAND DRIVE/HEAD CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR COUNT FEATURES Details of S.M.A.R.T. features are described in Section 9. 8.32 Standby (96h or E2) This command causes the Drive to set BSY, ...

Page 59

Wear Level (F5h) This command is effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with a ‘00h’ indicating Wear Level is not needed. defines the Wear Level command Byte ...

Page 60

Write Multiple Command (C5h) This command is similar to the Write Sectors command. The Drive sets BSY within 400ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains ...

Page 61

No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host. For multiple sectors, after the first ...

Page 62

S.M.A.R.T. Functionality The SSD support the following SMART commands, determined by the Feature Register value. Table 86: S.M.A.R.T. Features Supported Feature Operation D0h SMART Read Data D1h SMART Read Attribute Thresholds D2h SMART Enable/Disable Attribute D8h SMART Enable Operations ...

Page 63

The data structure returned is: Table 90: S.M.A.R.T. Data Structure Offset Value Description 0..1 0004h SMART structure version 2..361 Attribute entries (12 bytes each) 362 00h Off-line data collection status (no off-line data collection) 363 00h Self-test ...

Page 64

Erase Count Attribute This attribute gives information about the amount of flash block erases that have been performed. Table 92: Erase Count Attribute Offset Value Description 0 E5h Attribute ID – Erase Count Usage (vendor specific) 1..2 0002h Flags ...

Page 65

Table 96: UDMA CRC Errors Attribute Offset Value Description 0 C7h Attribute ID – UDMA CRC error rate 1..2 0002h Flags – Advisory type, value is updated during normal operation 3 64h Attribute value. This value is fixed at 100. ...

Page 66

Table 104: UDMA CRC Errors Attribute Offset Value Description 0 C7h Attribute ID – UDMA CRC error rate 1 00h No threshold for the UDMA CRC Errors Attribute 2..11 00h Reserved 9.5 S.M.A.R.T. Return Status This command checks the device ...

Page 67

Table 108: S.M.A.R.T. read remap data (Feature E0h) Task File Register COMMAND DRIVE/HEAD CYLINDER HI CYLINDER LOW SECTOR NUM SECTOR COUNT FEATURES The layout of the returned sectors is, with n the sector number from Table 109: ...

Page 68

Package mechanical Figure 14: SSD Drive Dimensions Dimension Height Width Max. Length Hole height 2. hole 3. hole Hole position Hole distance 2. hole 3. hole Screw head diameter Hole depth bottom Hole depth side 1. hole 4. hole ...

Page 69

Figure 15: Connector location Dimension Swissbit AG Swissbit reserves the right to change products or specifications without notice. Industriestrasse 4 CH-9552 Bronschhofen Switzerland mm 5.5 65.0 14.0 34.9 10.1 4.0 min 3.5 www.swissbit.com ...

Page 70

Declaration of Conformity Product Type: Solid State Drive (SSD) Brand Name: SWISSMEMORY Model Designation: SFPAxxxxQxxxxxx-x-xx-xxx-xxx Manufacturer: Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland The product complies with the requirements of the following directives: CENELEC EN 55022B :2000 + CISPR22B ...

Page 71

RoHS and WEEE update from Swissbit Dear Valued Customer Swissbit place great value on the environment and thus pay close attention to the diverse aspects of manufacturing environmentally and health friendly products. The European Parliament and the ...

Page 72

Swissbit is obliged to minimize the hazardous substances in the products. According to part of the Directive, manufacturers are obliged to make a self-declaration for all devices with RoHS. Swissbit carried out intensive tests to comply with the self-declaration. We ...

Page 73

Part Number Decoder 16GB Manuf. Memory Type. Product Type Density Platform Product Generation Memory Organization 13.1 Manufacturer 13.2 Memory Type 13.3 Product Type 13.4 Density 13.5 Platform 13.6 Product Generation 13.7 Memory Organization ...

Page 74

Temp. Option Industrial Temp. Range -40°C – 85°C Standard Temp. Range 0°C – 70°C 13.12 DIE Classification SLC MONO (single die package) SLC DDP SLC QDP 13.13 PIN Mode Normal nCE & R/nB Dual nCE & Dual R/nB 13.14 ...

Page 75

Swissbit SSD Marking specification 14 14.1 Top view Industrial Drive 14.1.1 Label content: Swissbit logo o Density o Master/Slave Pin description o CE logo o FCC logo o Pb-free logo o WEEE logo o Part number o Assembly lot information ...

Page 76

Revision History Table 110: Document Revision History Date Revision Revision Details 28-September-2010 1.00 Initial release Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, ...