SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 28

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 11: Ultra DMA Data-Out Burst Device Termination Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.3.2.4.10 Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in Figure 12: Ultra DMA Data-Out Burst Host
Termination Timing while timing parameters are specified in Table 22: Ultra DMA Data Burst Timing
Requirements and timing parameters are described in Table 23: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
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a) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
b) The host shall assert STOP no sooner than t
c)
d) The device shall negate -DDMARDY within t
e) If HSTROBE is negated, the host shall assert HSTROBE within t
f)
g) The host shall negate -DMACK no sooner than t
not negate STOP again until after the Ultra DMA burst is terminated.
The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
assert -DDMARDY again until after the Ultra DMA burst termination is complete.
No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
The host shall place the result of its CRC calculation on D[15:00] (see 6.3.2.5 ).
the device has negated DMARQ and -DDMARDY, and no sooner than t
CRC calculation on D[15:00].
Swissbit reserves the right to change products or specifications without notice.
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SS
LI
after it last generated an HSTROBE edge. The host shall
after the host has negated STOP. The device shall not
MLI
after the host has asserted HSTROBE and STOP and
LI
after the device has negated DMARQ.
P-120_data_sheet_PA-QxBO_Rev100.doc
DVS
after placing the result of its
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