SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 30

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Table 26: Equations for parallel generation of an Ultra DMA CRC
CRCIN0 = f16
CRCIN1 = f15
CRCIN2 = f14
CRCIN3 = f13
CRCIN4 = f12
CRCIN5 = f11 XOR f16
CRCIN6 = f10 XOR f15
CRCIN7 = f9 XOR f14
f1 = D00 XOR CRCOUT15
f2 = D01 XOR CRCOUT14
f3 = D02 XOR CRCOUT13
f4 = D03 XOR CRCOUT12
f5 = D04 XOR CRCOUT11 XOR f1
f6 = D05 XOR CRCOUT10 XOR f2
f7 = D06 XOR CRCOUT9 XOR f3
f8 = D07 XOR CRCOUT8 XOR f4
Notes:
An example of a CRC generator implementation is provided below in Figure 13: Ultra DMA Parallel CRC
Generator Example.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
6. The device shall then compare the CRC data from the host with the calculated value in its own CRC
7.
8. For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE
9. For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device
10. A host may send extra data words on the last Ultra DMA burst of a data out command. If a device
11. 11. The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 26 describes the equations for
1.
2.
3.
4.
calculation function. If the two values do not match, the device shall save the error and report it at
the end of the command. A subsequent Ultra DMA burst for the same command that does not have
a CRC error shall not clear an error saved from a previous Ultra DMA burst in the same command. If a
miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of
the command, the device shall report the first error that occurred.
For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in
the Error register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to
this error by re-issuing the command.
command): When a CRC error is detected during transmission of sense data the device shall
complete the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED
COMMAND). The device shall preserve the original sense data that was being returned when the CRC
error occurred. The device shall not report any additional sense data specific to the CRC error. The
host device driver may retry the REQUEST SENSE command or may consider this an unrecoverable
error and retry the command that caused the Check Condition.
shall complete the command with CHK set to one. The device shall report a Sense key of 04h
(HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall report
an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host drivers should retry the
command that resulted in a HARDWARE ERROR.
NOTE - If excessive CRC errors are encountered while operating in Ultra mode 2 or 1, the host should
select a slower Ultra mode. Caution: CRC errors are detected and reported only while operating in an
Ultra mode.
determines that all data has been transferred for a command, the device shall terminate the burst.
A device may have already received more data words than were required for the command. These
extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA
data out burst, the extra words shall be discarded by the device.
16-bit parallel generation of the resulting polynomial (based on a word boundary).
NOTE - Since no bit clock is available, the recommended approach for calculating CRC is to use a
word clock derived from the bus strobe. The combinational logic is then equivalent to shifting
sixteen bits serially through the generator polynomial where D00 is shifted in first and D15 is
shifted in last.
f=feedback
D[15:0] = Data to or from the bus
CRCOUT = 16-bit edge triggered result (current CRC)
CRCOUT[15:0] are sent on matching order bits of D[15:00]
Swissbit reserves the right to change products or specifications without notice.
CRCIN8 = f8 XOR f13
CRCIN9 = f7 XOR f12
CRCIN10 = f6 XOR f11
CRCIN11 = f5 XOR f10
CRCIN12 = f4 XOR f9 XOR f16
CRCIN13 = f3 XOR f8 XOR f15
CRCIN14 = f2 XOR f7 XOR f14
CRCIN15 = f1 XOR f6 XOR f13
f9 = D08 XOR CRCOUT7 XOR f5
f10 = D09 XOR CRCOUT6 XOR f6
f11 = D10 XOR CRCOUT5 XOR f7
f12 = D11 XOR CRCOUT4 XOR f1 XOR f8
f13 = D12 XOR CRCOUT3 XOR f2 XOR f9
f14 = D13 XOR CRCOUT2 XOR f3 XOR f10
f15 = D14 XOR CRCOUT1 XOR f4 XOR f11
f16 = D15 XOR CRCOUT0 XOR f5 XOR f12
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