SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 27

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 10: Ultra DMA Data-Out Burst Device Pause Timing
Notes:
6.3.2.4.9 Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing
diagram for the operation is shown in Figure 11: Ultra DMA Data-Out Burst Device Termination Timing. The
timing parameters are specified in Table 22: Ultra DMA Data Burst Timing Requirements and are described in
Table 23: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
1.
2.
a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra
b) The device shall initiate Ultra DMA burst termination by negating -DDMARDY.
c)
d) If the device negates -DDMARDY within t
e) The device shall negate DMARQ no sooner than t
f)
g) If HSTROBE is negated, the host shall assert HSTROBE within t
h) The host shall place the result of its CRC calculation on D[15:00] (see 6.3.2.5 ).
i)
j)
k) The device shall compare the CRC data received from the host with the results of its own CRC
The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after
-DDMARDY is negated.
After negating -DDMARDY, the device may receive zero, one, two, or three more data words from the host.
DMA burst has been transferred.
The host shall stop generating an HSTROBE edges within t
device shall be prepared to receive zero or one additional data words. If the device negates -
DDMARDY greater than t
prepared to receive zero, one or two additional data words. The additional data words are a result
of cable round trip delay and t
assert DMARQ again until after the Ultra DMA burst is terminated.
The host shall assert STOP within t
STOP again until after the Ultra DMA burst is terminated.
No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
The host shall negate -DMACK no sooner than t
the device has negated DMARQ and -DDMARDY, and no sooner than t
CRC calculation on D[15:00].
The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one
command.
Swissbit reserves the right to change products or specifications without notice.
SR
after the host has generated anHSTROBE edge, then the device shall be
RFS
timing for the host.
LI
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after the device has negated DMARQ. The host shall not negate
www.swissbit.com
SR
after the host has generated an HSTROBE edge, then the
MLI
RP
after the host has asserted HSTROBE and STOP and
after negating -DDMARDY. The device shall not
RFS
of the device negating -DDMARDY.
LI
after the device has negated DMARQ.
P-120_data_sheet_PA-QxBO_Rev100.doc
DVS
after placing the result of its
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