SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 14

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

6.3 Ultra DMA Mode
6.3.1 Ultra DMA Overview
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When
this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when
these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this
protocol is used there are no changes to other elements of the ATA protocol (e.g., Command Block Register
access).
The usage of signals in each of the modes is shown in Table 21: Signal Usage in PIO/MDMA vs. UDMA Mode
Table 21: Signal Usage in PIO/MDMA vs. UDMA Mode
UDMA Signal
DMARQ
DMACK
STOP
HDMARDY(R)
HSTROBE(W)
DDMARDY(W)
DSTROBE(R)
DATA
ADDRESS
CSEL
INTRQ
Card Select
Notes:
Several signal lines are redefined to provide different functions during an Ultra DMA burst. These lines
assume these definitions when:
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of -
DMACK by the host at the termination of an Ultra DMA burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same
agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe
signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-
out burst.
During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to
allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to
latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to
the same frequency as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the
device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be
used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by
a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA
mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be
satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software
reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable
reverting to defaults command has been issued. The device may revert to a Multiword DMA mode if a SET
FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any
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1.
2. The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA
3. The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA
4. The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
1.
2. a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. the device asserts (-)DMARQ, and
4. the host asserts -DMACK.
The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
Read command.
Write command.
an Ultra DMA mode is selected, and
33, 35, 36
37, 38
3 - 18
Swissbit reserves the right to change products or specifications without notice.
Pin
21
29
23
25
27
28
31
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Bidir
IORDY
-IOWR
MDMA
-IORD
PIO /
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-CS0, -CS1
-DMACK
D[15:00]
DMARQ
A[02:00]
HSTROBE(W)
-DDMARDY(W)
DSTROBE(R)
INTRQ
-HDMARDY(R)
-CSEL
STOP
UDMA
1
1. 2. 4
1, 3, 4
1, 2
1, 3
UDMA write clock from host
UDMA read clock from drive
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