SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 20

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 3: Ultra DMA Data-In Burst Initiation Timing
Notes: The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and -IOWR:STOP signal
lines are not in effect until DMARQ and -DMACK are asserted.
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j)
k) The host shall negate STOP and assert -HDMARDY within t
l)
m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when
n) To transfer the first word of data the device shall negate DSTROBE within t
The device may assert DSTROBE t
DSTROBE the device shall not release DSTROBE until after the host has negated -DMACK at the end of
an Ultra DMA burst.
STOP and asserting -HDMARDY, the host shall not change the state of either signal until after
receiving the first transition of DSTROBE from the device (i.e., after the first data word has been
received).
The device shall drive D[15:00] no sooner than t
STOP, and asserted -HDMARDY.
the device first drives D[15:00] in step (j).
negated STOP and asserted -HDMARDY. The device shall negate DSTROBE no sooner than t
driving the first word of data onto D[15:00].
Swissbit reserves the right to change products or specifications without notice.
ZIORDY
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after the host has asserted -DMACK. Once the device has driven
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ZAD
after the host has asserted -DMACK, negated
ENV
after asserting -DMACK. After negating
P-120_data_sheet_PA-QxBO_Rev100.doc
FS
after the host has
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DVS
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after
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