SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 13

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

6.2 MDMA Mode
Figure 2: True IDE Multi-Word DMA Mode Read/Write waveforms
Table 20: True IDE Multi-Word DMA Mode Read/Write timing
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Parameter
Cycle time (min)
-IORD / -IOWR asserted width (min)
-IORD data access (max)
-IORD data hold (min)
-IORD/-IOWR data setup (min)
-IOWR data hold (min)
DMACK to –IORD/-IOWR setup (min)
-IORD / -IOWR to –DMACK hold (min)
-IORD Low width (min)
-IOWR Low width (min)
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CS(1:0) valid to –IORD / -IOWR
CS(1:0) hold
-DMACK
1.
2.
3.
4.
1.
The maximum load on –IOCS16 is 1 LSTTL with a 50pF total load.
t
or command inactive time. The actual cycle time equals the sum of the actual command inactive time. The three timing
requirements of t0, t
implementation can ensure that t0 is equal to or greater than the value reported in the devices identify drive
implementation should support any legal host implementation.
This parameter specifies the time from the falling edge of –IORD to the moment when the drive (tri-state).
t
t
recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the
actual command active time and the actual command inactive time. The timing requirements of
respected.
either t
data. A Drive implementation shall support any legal host implementation.
0
0
7
and t
is the minimum total cycle time, t
is the minimum total cycle time.
–DMARQ
–DMACK
8
D
or
apply only to modes 0, 1 and 2. The –IOCS16 signal is not valid for other modes.
T
t
KR
0
is higher than
/t
KW
Swissbit reserves the right to change products or specifications without notice.
, or both, to ensure that t
2
, and t
2i
t
D
have to be met. The requirement is greater than the sum of t
+ t
KR
T
2
or
D
is the minimum command active time, and t
is the minimum command active time.
t
D
+ t
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0
KW
is equal to or higher than the value reported in the devices identify device
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, for input and output cycles respectively. This means the host can lengthen
Symbol
t
t
KW
t
t
KR
t
t
D
0
t
t
t
t
t
t
t
LW
t
LR
t
G
M
(1)
E
F
H
N
Z
(1)
J
I
(1)
(1)
T
KR
2i
and
is the minimum command recovery time
P-120_data_sheet_PA-QxBO_Rev100.doc
Mode 0
t
KW
(ns)
480
215
150
100
215
120
20
20
50
40
50
15
20
5
0
are the minimum command
2
and t
t
2i
0
. This means a host
, t
D
, t
(ns)
150
80
60
30
15
50
50
40
40
30
10
25
KR
5
0
5
1
, and t
Page
Revision: 1.00
KW
must be
13 of 76
(ns)
120
70
50
20
10
25
25
35
35
25
10
25
2
5
0
5