SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 9

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

5 Electrical interface
5.1 Electrical description
The SSD is connected with a standard IDE 44 pin connector (pitch 2.00mm). The power is connected at pin
41-44. The Master card can be configured as Master or slave with a jumper at pins A – D.
The signal/pin assignments and descriptions are listed in Table 11 Low active signals have a ‘-’ prefix.
Pin types are Input, Output or Input/Output. Inputs are signals sourced from the host while Outputs are
signals sourced from the Drive.
The configuration of the SSD is controlled using the standard IDE configuration registers starting at address
200h in the Attribute Memory space of the memory drive.
Table 11: Pin Assignment, Type, and description
Reset signal from host. Reset is
This is a Read strobe generated
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
low 8 lines transfer commands
Pins 3 through 18 (16 lines (15-
bus and strobes the data from
the controller into the host on
0) carry the data between the
I/O data or status on the host
commands on the drive data
by the host. The signal gates
controller and the host. The
This I/O Write strobe pulse is
bus into the drive controller
up and inactive thereafter.
interface. The clocking will
registers when the drive is
positive edge of the signal
between the host and the
the low to high transition
configured to use the I/O
occur on the negative to
and the ECC information
used to clock I/O data or
Signal description
active on power
(trailing edge).
(trailing edge).
controller.
Not used.
Ground
Swissbit reserves the right to change products or specifications without notice.
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
HDMARDY
HSTROBE
-IOWR/
DMARQ
-RESET
Signal
Name
-IORD
STOP
GND
D06
D05
D04
D03
D02
D00
D07
D01
-
[e-mail]
www.swissbit.com
23
25
13
15
19
21
11
17
5
9
Pin Num
3
7
1
20
26
10
14
16
18
22
24
12
4
6
8
2
Signal
Name
GND
GND
GND
GND
D08
D09
Key
D10
D13
D14
D15
D11
D12
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P-120_data_sheet_PA-QxBO_Rev100.doc
controller and the host. The low 8
ECC information between the host
lines transfer commands and the
Pins 3 through 18 (16 lines (15-0)
carry the data between the
and the controller.
Signal description
Connector key
Ground
Ground
Ground
Ground
Revision: 1.00
Page
9 of 76