ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 10

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ISP1582BS

Manufacturer Part Number
ISP1582BS
Description
IC USB CTRL HI-SPEED 56HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1582BS

Applications
USB Host/Peripheral Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Mounting Type
Surface Mount
For Use With
ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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NXP Semiconductors
Table 5.
Table 6.
Table 7.
AN10039_4
Application note
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
ATA mode
0
ISP1583 DMA Configuration register: bit allocation
ISP1583 DMA Hardware register: bit allocation
DMA configuration
Master
0
DIS_XFER_
2.5 Initializing the DMA Configuration and Hardware registers
CNT
R/W
R/W
15
7
0
0
7
0
0
-
-
-
ENDIAN[1:0]
reserved
DMA mode PIO mode
Not used
Next, you configure the DMA Configuration register (see
register (see
application, some associated registers must be programmed.
The ISP1582/83 can be configured to various operation modes, depending on the
combination of the various bits in the DMA Configuration and DMA Hardware registers.
Table 7
Remark: Only ISP1583 supports DMA master and ATA mode.
R/W
14
6
6
0
0
-
-
-
-
-
-
illustrates valid combinations.
Not used
Table
EOT_POL
reserved
MODE
ATA_
R/W
R/W
6) to either GDMA or mass storage application. Based on the
13
0
0
5
5
0
0
-
-
-
Rev. 04 — 21 December 2006
DIS_XFER
_CNT
0
MASTER
R/W
R/W
DMA_MODE[1:0]
12
0
0
4
4
0
0
-
-
-
Mode
0
ACK_POL
R/W
R/W
R/W
ISP1582/83 Firmware Programming Guide
11
0
0
3
0
0
3
0
0
MODE[1:0]
Width
1
DREQ_
POL
R/W
R/W
R/W
Table
10
0
0
2
0
0
2
1
1
Description
GDMA slave mode
DMA transfer counter
DIOR as read strobe
DIOW as write strobe
16-bit data bus
5) and DMA Hardware
PIO_MODE[2:0]
reserved
WRITE_
POL
R/W
R/W
AN10039
© NXP B.V. 2006. All rights reserved.
9
0
0
1
1
0
0
-
-
-
READ_POL
WIDTH
R/W
R/W
R/W
8
0
0
0
1
1
0
0
0
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