ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 47

• Manufacturer Part Number: ISP1582BS
• Description: IC USB CTRL HI-SPEED 56HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1582BS

• Applications: USB Host/Peripheral Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Mounting Type: Surface Mount
• For Use With: ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
AN10039_4
Application note
Fig 33. Handling PIO read
Initialize the Endpoint Index
register to the respective IN
PIO_Bytes_Remaining != 0
Issue the CPLD PIO Reset
PIO_Bytes_Remaining = 0
Enable CPLD PIO mode
PIO_Bytes_Remaining =
This_buffer_remain > 64
This_buffer_remain = 0
PIO_maxpacket_size =
PIO_Bytes_Remaining
PIO_Bytes_remaining
This_buffer_remain =
This_buffer_remain
PIO_MaxPaketSize
This_tranfer_size =
This_buffer_remain
This_buffer_size =
This_transfer_size
FileSize.Size
Is the device
full-speed?
command
endpoint
Start
512
Yes
Yes
No
No
No
A
>
PIO_maxpacket_size =
No
Yes
D
No
This_buffer_remain - = 64
This_buffer_size = 64
Yes
C
64
B
PIO_Bytes_remaining - =
Yes
PIO_MaxPacketSize
PIO_MaxPacketSize
Rev. 04 — 21 December 2006
This_tranfer_size =
EP0SETUP are from
which the Interrupt
Reason register is
interrupt routine
the variable into
Bits SUSP and
copied in the
BUS_RESET interrupt
BUS_RESET is a flag
Validate the buffer by setting bit
VENDP in the Control Function
which is set on the
register for short packet
Yes
Yes
Yes
ISP1582/83 Firmware Programming Guide
Write to the Data Port register LSB from the internal
Write to the Data Port register MSB from the
CPLD PIO Read MSB to the internal RAM
CPLD PIO Read LSB to the internal RAM
C
Wait if the Buffer Status register == 3
(exit on SUSP, BUS_RESET,
Increment Count_PIO
Increment Count_PIO
Increment Count_PIO
Increment Count_PIO
PIO_MaxPacketSize
This_transfer_size
this_buffer_size
this_buffer_size
Count_PIO = 0
Count_PIO = 0
internal RAM
BUS_RESET
EP0SETUP)
Count_PIO
Count_PIO
SUSP OR
RAM
Stop
Yes
No
No
No
A
<
<
<
AN10039
© NXP B.V. 2006. All rights reserved.
No
B
D
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