ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 45

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ISP1582BS

Manufacturer Part Number
ISP1582BS
Description
IC USB CTRL HI-SPEED 56HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1582BS

Applications
USB Host/Peripheral Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Mounting Type
Surface Mount
For Use With
ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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NXP Semiconductors
AN10039_4
Application note
Fig 31. Handling PIO or GDMA read
No
Initialize the DMA Endpoint register to
Initialize the DMA transfer counter to
Initialize the Endpoint Index register
Initialize the CPLD DMA controller
to value not equal to the DMA
DMA_Test_Mode == GDMA
DMA_Test_Mode == MDMA
the respective IN endpoint
DMA_Test_Mode != PIO
Set CPLD DMA mode
Reset the CPLD DMA
for Slave Write mode
Stop the CPLD DMA
Endpoint register
Is master mode
FileSize.Size
PIO_Read
controller
controller
Handle
Start
Stop
Yes
No
No
No
DMA command register =
MDMA_Read command
Reset internal variable
DMA_XFER_OK == 0
DMA_XFER_OK = 0
controller for Master Read
Yes
Initialize the CPLD DMA
Initialize the CPLD DMA
counter to FileSize.SIze
Yes
Rev. 04 — 21 December 2006
No
mode
Yes
DMA command register =
GDMA_Read command
Write to the DMA command
register with DMA_REST
BUS_RESET ==1 OR
Reinitialize the DMA
Yes
EP0SETUP ==1
SUSP ==1 OR
ISP1582/83 Firmware Programming Guide
Yes
No
the variable to which the DMA
copied in the interrupt routine
Bits SUSP and EP0SETUP are
from the variable to which the
copied in the interrupt routine
Bit DMA_XFER_OK is from
Interrupt reason register is
Interrupt reason register is
BUS_RESET is a flag
AN10039
© NXP B.V. 2006. All rights reserved.
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