ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 6

• Manufacturer Part Number: ISP1582BS
• Description: IC USB CTRL HI-SPEED 56HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1582BS

• Applications: USB Host/Peripheral Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Mounting Type: Surface Mount
• For Use With: ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 1.
[1]
AN10039_4
Application note
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Value depends on the status of the V
ISP1583 Mode register: bit allocation
CLKAON
TEST2
2.2 Initializing the Mode register
2.3 Initializing the Interrupt Configuration register
R/W
15
R
7
0
0
-
-
After the power-on reset, the processor initializes the Mode register (see
register can be programmed, depending on the application.
The DMACLKON bit of the Mode register determines whether the clock must be supplied
to the DMA core of the ISP1582/83. Disabling the bit at initialization saves power. The
DMA clock can be switched on when DMA is required using the DMACLKON bit.
Power can also be saved by disabling clock CLKAON during suspend mode. It is
recommended that you use this power-saving mechanism to save power when the
ISP1582/83 is configured to bus-powered applications. Next, set the global interrupt
enable (bit GLINTENA) to enable the interrupt mechanism of the ISP1582/83. The
ISP1582/83 allows you to wake up the system from suspend mode by toggling the chip
select (pin CS_N) of the ISP1582/83.
The ISP1582/83 allows you to design systems to support sleep mode, in which power to
the ISP1582/83 is turned off to save power. The PWRON bit in the Mode register
configures the ISP1582/83 into two modes of operation when it is in the suspend state.
When the bit is set to logic 0, the firmware must issue an unlock command to the
ISP1582/83 before any write operation to a register can be performed. This prevents
accidental writing to registers when the processor wakes up from power-saving mode.
The SoftConnect feature (bit SOFTCT) is used to connect the pull-up resistor to the DP
line of the ISP1582/83. This affords you complete discretion on when to connect and
disconnect from the USB bus. The SOFTCT bit is used together with V
VBUSSTAT) that reflects whether the USB cable is plugged in or out.
After the Mode register is set, the Interrupt Configuration register (see
initialized. This register controls how an interrupt is generated for the control pipe, IN
endpoint and OUT endpoint.
SNDRSU
TEST1
R/W
14
R
6
0
0
-
-
BUS
pin.
GOSUSP
TEST0
R/W
13
R
5
0
0
-
-
Rev. 04 — 21 December 2006
SFRESET
R/W
12
4
0
0
-
-
-
GLINTENA
unchanged
reserved
R/W
ISP1582/83 Firmware Programming Guide
11
3
0
-
-
-
WKUPCS
R/W
10
2
0
0
-
-
-
DMACLK
PWRON
R/W
R/W
ON
AN10039
Table
© NXP B.V. 2006. All rights reserved.
9
0
0
1
0
0
BUS
Table
(bit
2) is
VBUSSTAT
unchanged
1). This
SOFTCT
R/W
[1]
[1]
R
8
0
0
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