ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 18

• Manufacturer Part Number: ISP1582BS
• Description: IC USB CTRL HI-SPEED 56HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1582BS

• Applications: USB Host/Peripheral Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Mounting Type: Surface Mount
• For Use With: ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 12.
Table 13.
AN10039_4
Application note
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Buffer Length register: bit allocation
Control Function register: bit allocation
R/W
R/W
15
7
0
0
7
0
0
-
-
-
FIFO, the buffer length is a means for the firmware to auto-validate the FIFO once the
value is reached. It is used when data to be sent in the IN endpoint is a short packet.
In the control function, the DSEN bit is for the ISP1582/83 to proceed to the data stage. If
the set-up token is with a data OUT stage, the firmware must set the DSEN bit to the
ISP1582/83 for the device to generate an ACK handshake to the OUT endpoint. This bit
also governs the IN endpoint data. An IN endpoint after a set-up token with the data IN
stage will not be sent to the USB bus even when the VENDP bit is issued. Therefore, the
DSEN bit must be set for the ISP1582/83 to proceed to the data stage of the setup.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the device
and the IN token is acknowledged by the PC host.
The status stage is achieved by setting the STATUS bit in the Control Function register.
On setting the STATUS bit, the endpoint will generate a zero-length packet to the IN
token and send an ACK for the OUT token. The status stage will not generate the control
IN endpoint interrupt.
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
reserved
R/W
R/W
14
6
0
0
6
0
0
-
-
-
R/W
R/W
13
5
0
0
5
0
0
-
-
-
Rev. 04 — 21 December 2006
CLBUF
DATACOUNT[15:8]
R/W
R/W
DATACOUNT[7:0]
R/W
12
4
0
0
0
0
4
0
0
VENDP
R/W
R/W
R/W
ISP1582/83 Firmware Programming Guide
11
3
0
0
0
0
3
0
0
DSEN
R/W
R/W
R/W
10
2
0
0
0
0
2
0
0
STATUS
R/W
R/W
R/W
AN10039
© NXP B.V. 2006. All rights reserved.
1
0
0
9
0
0
1
0
0
STALL
R/W
R/W
R/W
17 of 49
0
0
0
8
0
0
0
0
0