ISP1582BS ST-Ericsson Inc, ISP1582BS Datasheet - Page 13

• Manufacturer Part Number: ISP1582BS
• Description: IC USB CTRL HI-SPEED 56HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1582BS

• Applications: USB Host/Peripheral Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Mounting Type: Surface Mount
• For Use With: ISP1582 PCI EVALKIT - PCI BUS EVAL KIT ISP1582
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 8.
AN10039_4
Application note
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Endpoint MaxPacketSize register: bit allocation
2.6 Initializing DMA burst counter
2.7 Initializing DMA interrupt enable
2.8 Initializing the ISP1582/83 endpoint
R/W
15
7
0
0
-
-
-
When DIS_XFER_CNT is set to logic 1, the DMA transfer counter is not in use, and the
DMA termination is done using the input signal of pin EOT. This mode is called EOT
mode. The polarity of pin EOT can be set using the EOT_POL bit of the DMA Hardware
register.
The DMA burst counter is initialized in multiples of two for 16-bit mode. DREQ is
asserted and de-asserted based on the value in the DMA Burst Counter register.
The IEDMA bit in the Interrupt Enable register must be logic 1 to enable DMA interrupts
on the INT pin. The respective bits of the DMA Interrupt Enable register are set to logic 1
to enable interrupt on the INT pin. If the bits are set to logic 0, the interrupt status is
reflected on the DMA Interrupt Reason register but the interrupt does not appear on the
INT pin.
The endpoint FIFO configuration is done using the Endpoint MaxPacketSize register (see
Table
register (see
For the same endpoint number, ensure that initialization is done for both the IN and OUT,
even if only IN or OUT is used.
reserved
8) and the Endpoint Type register
R/W
14
6
0
0
-
-
-
Table
R/W
10).
13
5
0
0
-
-
-
Rev. 04 — 21 December 2006
R/W
R/W
12
0
0
4
0
0
NTRANS[1:0]
FFOSZ[7:0]
(Table
R/W
R/W
ISP1582/83 Firmware Programming Guide
11
0
0
3
0
0
9), and indexed using the Endpoint Index
R/W
R/W
10
0
0
2
0
0
FFOSZ[10:8]
R/W
R/W
AN10039
© NXP B.V. 2006. All rights reserved.
9
0
0
1
0
0
R/W
R/W
12 of 49
8
0
0
0
0
0