ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 138
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
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21.6
21.6.1
138
Serial Downloading
ATtiny25/45/85
Serial Programming Algorithm
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 21-1. Serial Programming and Verify
Notes:
Table 21-8.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See
Figure 21-2
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
Symbol
MOSI
MISO
SCK
CLKI pin.
and
Pin Mapping Serial Programming
Figure 21-3
MOSI
MISO
for timing details.
SCK
Pins
PB0
PB1
PB2
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
GND
(1)
I/O
O
I
I
VCC
+4.5 - 5.5V
Table 21-8 on page
Serial Data out
ck
ck
Serial Data in
Description
Serial Clock
>= 12 MHz
>= 12 MHz
7598H–AVR–07/09
138, the pin
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