ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 42

• Manufacturer Part Number: ATtiny25 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny25 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.9.1
42
ATtiny25/45/85
Watchdog Timer Control Register – WDTCR
• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable
When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the
Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed
instead of a reset if a timeout in the Watchdog Timer occurs.
If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful
for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,
the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after
each interrupt.
Table 8-6.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. This bit must also be set when
changing the prescaler bits.
Watchdog Timer” on page 44.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 44.
Bit
Read/Write
Initial Value
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
WDE
0
0
1
1
ten to WDE even though it is set to one before the disable operation starts.
Watchdog Timer Configuration
WDIF
WDIE
R/W
7
0
0
1
0
1
See “Timed Sequences for Changing the Configuration of the Watchdog
WDIE
R/W
6
0
Watchdog Timer State
Stopped
Running
Running
Running
See “Timed Sequences for Changing the Configuration of the
WDP3
R/W
5
0
WDCE
R/W
4
0
WDE
R/W
X
3
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt
WDP1
R/W
1
0
WDP0
R/W
0
0
7598H–AVR–07/09
WDTCR