ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 96

• Manufacturer Part Number: ATtiny25 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny25 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16. Universal Serial Interface – USI
16.1
96
Overview
ATtiny25/45/85
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load. The main features of the USI are:
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•
•
•
•
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A simplified block diagram of the USI is shown on Figure 16-1. For the actual placement of I/O
pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
Figure 16-1. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the Serial
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock
source.
Two-wire Synchronous Data Transfer (Master or Slave, f
Three-wire Synchronous Data Transfer (Master or Slave f
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“USI Register Descriptions” on page
“Pinout ATtiny25/45/85” on page
USIDR
USIDB
USISR
USICR
2
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
103.
[1]
2. CPU accessible I/O Registers, including I/O
TIM0 COMP
0
1
SCLmax
SCKmax
Two-wire Clock
Control Unit
= f
= f
CK
CK
/16)
CLOCK
/4)
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
7598H–AVR–07/09