ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 89
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 89 of 196
- Download datasheet (4Mb)
14.1.9
14.1.10
7598H–AVR–07/09
PLL Control and Status Register - PLLCSR
Timer/Counter1 Initialization for Asynchronous Mode
In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match
occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C.
Clearing the Timer/Counter1 with the bit CTC1 does not generate an overflow.
When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set
(one), the Timer/Counter1 Overflow interrupt is executed.
• Bit 0 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 7- LSM: Low Speed Mode
The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low
speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled
down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.7 volts,
because the Timer/Counter1 is not running fast enough on low voltage levels. It is highly recom-
mended that Timer/Counter1 is stopped whenever the LSM bit is changed.
• Bit 6.. 3- Res : Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 2- PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as
Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and
system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is
set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. The bit PCKE can
only be set, if the PLL has been enabled earlier.
• Bit 1- PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0- PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK
for Timer/Counter1. After the PLL is enabled, it takes about 100 micro seconds for the PLL to
lock.
To change Timer/Counter1 to the asynchronous mode, first enable PLL, wait 100 µs before poll-
ing the PLOCK bit until it is set, and then set the PCKE bit.
Bit
$27 ($27)
Read/Write
Initial value
LSM
R/W
7
0
R
6
0
-
5
R
0
-
R
4
0
-
R
3
0
-
PCKE
R/W
2
0
ATtiny25/45/85
PLLE
R/W
0/1
1
PLOCK
R
0
0
PLLCSR
89
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