ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 83

• Manufacturer Part Number: ATtiny25 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny25 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7598H–AVR–07/09
Figure 14-3. Timer/Counter1 Block Diagram
Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt
Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1
and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt
Mask Register - TIMSK.
The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C
as the data source to be compared with the Timer/Counter1 contents. In normal mode the Out-
put Compare functions are operational with all three output compare registers. OCR1A
determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal
mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can
generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the
Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an
overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in
the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF
to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in
normal mode.
In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter
value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are
generated. In PWM mode, the Timer Counter counts up to the value specified in the output com-
pare register OCR1C and starts again from $00. This feature allows limiting the counter “full”
value to a specified value, lower than $FF. Together with the many prescaler options, flexible
PWM frequency selection is provided.
obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz
in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.
8-BIT DATABUS
COMPARE REGISTER
TIMER/COUNTER1
8-BIT COMPARATOR
REGISTER (TIMSK)
TIMER/COUNTER1
TIMER INT. MASK
T/C1 OUTPUT
T/C1 OVER-
FLOW IRQ
(OCR1A)
(TCNT1)
T/C1 COMPARE
MATCH A IRQ
T/C CLEAR
REGISTER (TIFR)
TIMER INT. FLAG
T/C1 COMPARE
MATCH B IRQ
COMPARE REGISTER
8-BIT COMPARATOR
T/C1 OUTPUT
(OCR1B)
Table 14-6
DEAD TIME GENERATOR
OC1A
(PB1)
lists clock selection and OCR1C values to
REGISTER 1 (TCCR1)
T/C1 CONTROL
T/C CONTROL
LOGIC
OC1A
(PB0)
COMPARE REGISTER
OC1B
DEAD TIME GENERATOR
(PB4)
8-BIT COMPARATOR
T/C1 OUTPUT
ATtiny25/45/85
(OCR1C)
GLOBAL T/C CONTROL
REGISTER (GTCCR)
OC1B
(PB3)
CK
PCK
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