ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 58
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 58 of 196
- Download datasheet (4Mb)
10.4
10.4.1
10.4.2
10.4.3
11. External Interrupts
58
Register Description for I/O-Ports
ATtiny25/45/85
Port B Data Register – PORTB
Port B Data Direction Register – DDRB
Port B Input Pins Address – PINB
The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that,
if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out-
puts. This feature provides a way of generating a software interrupt. Pin change interrupts PCI
will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins con-
tribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held
low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an
I/O clock, described in
INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part
also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except
Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
“System Clock and Clock Options” on page
R
R
R
7
–
0
7
–
0
7
–
0
“Clock Systems and their Distribution” on page
R
R
R
6
–
0
6
0
6
–
0
–
PORTB5
PINB5
DDB5
R/W
R/W
R/W
N/A
5
0
5
0
5
PORTB4
PINB4
DDB4
R/W
R/W
R/W
N/A
4
0
4
4
0
21.
PORTB3
PINB3
DDB3
R/W
R/W
R/W
N/A
3
0
3
0
3
PORTB2
PINB2
DDB2
R/W
R/W
R/W
N/A
2
0
2
2
0
PORTB1
PINB1
21. Low level interrupt on
DDB1
R/W
R/W
R/W
N/A
1
0
1
0
1
PORTB0
PINB0
DDB0
R/W
R/W
R/W
N/A
0
0
0
0
0
7598H–AVR–07/09
PORTB
DDRB
PINB
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