AD7194

Manufacturer Part NumberAD7194
Description8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
ManufacturerAnalog Devices
AD7194 datasheet
 


Specifications of AD7194

Resolution (bits)24bit# Chan8
Sample Raten/aInterfaceSer,SPI
Analog Input TypeDiff-UniAin Range(2Vref/PGA Gain) p-p
Adc ArchitectureSigma-DeltaPkg TypeCSP
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FEATURES
Fast settling filter option
8 differential/16 pseudo differential input channels
RMS noise: 11 nV at 4.7 Hz (gain = 128)
15.5 noise-free bits at 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AV
: 3 V to 5.25 V
DD
DV
: 2.7 V to 5.25 V
DD
Current: 4.65 mA
Temperature range: −40°C to +105°C
Package: 32-lead LFCSP
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
PLC/DCS analog input modules
Data acquisition
Strain gage transducers
AIN1/P3
AIN2/P2
AIN3/P1/REFIN2(+)
AIN4/P0/REFIN2(–)
AIN5
AIN16
AINCOM
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
8-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7194 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have eight differential inputs or
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
can be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. For applications that
require all conversions to be settled, the AD7194 includes zero
latency.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is housed in a 32-lead
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
AV
AGND
DV
DGND
REFIN1(+)
REFIN1(–)
DD
DD
AD7194
AV
DD
MUX
Σ-Δ
PGA
ADC
AGND
TEMP
SENSOR
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD7194
REFERENCE
DETECT
DOUT/RDY
SERIAL
INTERFACE
DIN
AND
CONTROL
SCLK
LOGIC
CS
CLOCK
CIRCUITRY
MCLK1 MCLK2
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.

AD7194 Summary of contents

  • Page 1

    ... Chromatography Medical and scientific instrumentation GENERAL DESCRIPTION The AD7194 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC ...

  • Page 2

    ... AD7194 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution ............................................................ 15 4 Sinc Chop Disabled ................................................................... 15 3 Sinc Chop Disabled ................................................................... 16 Fast Settling ...

  • Page 3

    ... Rev Page AD7194 , REFINx(−) = AGND Test Conditions/Comments Chop disabled 4 Chop enabled, sinc filter 3 Chop enabled, sinc filter 3 4 FS[9:0] > 1, sinc filter 3 3 FS[9:0] > 4, sinc ...

  • Page 4

    ... AD7194 Parameter Min 2 Normal Mode Rejection 4 Sinc Filter Internal Clock @ 50 Hz 100 External Clock @ 50 Hz 120 120 @ 60 Hz 120 3 Sinc Filter Internal Clock @ 50 Hz External Clock @ 50 Hz 100 @ 50 Hz ...

  • Page 5

    ... V V 0.4 V 0.4 V +10 μ Offset binary Rev Page AD7194 1 Test Conditions/Comments REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AV − 1.25 V)/gain when gain > External clock Internal clock Applies after user calibration at 25°C Bipolar mode Analog inputs must be buffered and chop ...

  • Page 6

    ... AD7194 Parameter Min 2 SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration −1.05 × FS Limit Input Span 0.8 × POWER REQUIREMENTS Power Supply Voltage AV − AGND − DGND 2.7 DD Power Supply Currents AI Current DD DI Current Temperature range: −40°C to +105°C. ...

  • Page 7

    ... SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high CS falling edge to SCLK active edge setup time Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time ) and timed from a voltage level of 1 limits AD7194 4 ...

  • Page 8

    ... AD7194 Circuit and Timing Diagrams DOUT/RDY (O) SCLK (I) I (1.6mA WITH DV SINK 100µA WITH OUTPUT 1.6V PIN 50pF I (200µA WITH DV SOURCE 100µA WITH DV DD Figure 2. Load Circuit for Timing Characterization CS ( MSB SCLK ( INPUT OUTPUT Figure 3 ...

  • Page 9

    ... Package Type −0 +0.3 V 32-Lead LFCSP −0 0 −0 0 ESD CAUTION −0 0 −0 0 −40°C to +105°C −65°C to +150°C 150°C 260°C Rev Page AD7194 θ θ Unit JA JC 32.5 32.71 °C/W ...

  • Page 10

    ... Analog Input Pin. 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point. AIN1/ AIN2/P2 AIN3/P1/REFIN2(+) 3 22 DGND AD7194 AIN4/P0/REFIN2(– AGND TOP VIEW AINCOM 5 20 AIN16 (Not to Scale AIN15 AGND AIN5 7 18 REFIN1(–) AIN6 ...

  • Page 11

    ... Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7194 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state low ...

  • Page 12

    ... AD7194 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,952 8,387,950 8,387,948 8,387,946 8,387,944 8,387,942 8,387,940 8,387,938 8,387,936 8,387,934 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, REF DD Gain = 128, Chop Disabled, Sinc 200 150 100 50 0 8,387,936 8,387,940 8,387,944 8,387,938 8,387,942 8,387,946 CODE Figure 7 ...

  • Page 13

    ... Rev Page AD7194 –40 – 100 TEMPERAUTRE (°C) –40 – 100 TEMPERATURE (°C) Figure 16. Gain vs. Temperature (Gain = 1) –40 –20 ...

  • Page 14

    ... AD7194 GAIN = 1 GAIN = 8 16 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 100 OUTPUT DATA RATE (Hz) 4 Figure 18. Noise-Free Resolution (Sinc Filter, Chop Disabled GAIN = 1 GAIN = 8 GAIN = 16 12 GAIN = 32 GAIN = 64 GAIN = 128 100 OUTPUT DATA RATE (Hz) 3 Figure 19 ...

  • Page 15

    ... RMS NOISE AND RESOLUTION The following tables show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7194 for various output data rates and gain settings with 4 3 chop disabled for the sinc and sinc filters and for fast settling mode ...

  • Page 16

    ... AD7194 3 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Output Data Filter Word (Decimal) Rate (Hz) 1023 4.7 640 7.5 480 150 16 300 5 960 2 2400 1 4800 Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Output Data ...

  • Page 17

    ... Gain 260 180 100 470 280 190 950 540 360 1000 580 390 1500 850 580 2000 1200 850 1 Gain 23.5 (21.2) 23.2 (20.7) 23.3 (20.6) 23.1 (20.3) 22.8 (20.1) 22.3 (19.6) 22 (19.3) 21.9 (19.1) 21.4 (18.7) 21.9 (19.3) 21.8 (19) 21.3 (18.6) 21.5 (18.7) 21.2 (18.5) 20.7 (18) 21 (18.3) 20.6 (18) 20.1 (17.5) AD7194 128 120 128 70 130 300 330 510 740 128 22.6 (20.1) 21.8 (19.2) 20.7 (18) 20.5 (17.9) 19.8 (17.2) 19.3 (16.7) ...

  • Page 18

    ... AD7194 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 15. Register Summary Register Addr. Dir. Default Communications ...

  • Page 19

    ... CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CR4 CR3 CR2 RS1(0) RS0(0) CREAD(0) Rev Page AD7194 CR1 CR0 0(0) 0(0) Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits ...

  • Page 20

    ... AD7194 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation read operation, and SR7 SR6 SR5 RDY(1) ...

  • Page 21

    ... MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7194. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7194 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7194. ...

  • Page 22

    ... MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7194 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the fast-settling filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled ...

  • Page 23

    ... Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided Power-down mode. In power-down mode, all AD7194 circuitry is powered down. The external crystal, if selected, remains active Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete ...

  • Page 24

    ... AD7194 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel ...

  • Page 25

    ... CON18 Pseudo Pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7194 is configured to have 16 pseudo differential analog inputs with AINCOM as the common negative terminal. Bits CH7 to CH4 select the positive input terminal while bits CH3 to CH0 have no effect. When the pseudo bit is set to 0, channel selection is controlled using the CH7 to CH0 bits ...

  • Page 26

    ... AD7194 Channel Selection (Pseudo Bit = 0) Table 22. Positive Input Selection Positive Input Enable Bits in Positive the Configuration Register Input Enabled CH7 CH6 CH5 CH4 AIN(+) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 ...

  • Page 27

    ... LSBs of the status register (CHD3 to CHD0) identify the channel from which the conversion originated. ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 The identification number for the AD7194 is stored in the ID register. This is a read-only register. GP7 GP6 GP5 ...

  • Page 28

    ... The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7194 must be placed in power-down mode or idle mode when writing to the offset register. FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC ...

  • Page 29

    ... Clock The AD7194 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7194. The internal clock can also be made available on a pin if a clock source is required for external circuitry. ...

  • Page 30

    ... The analog input range must be limited to ±(AV because the PGA requires some headroom. Therefore AD7194 3.75 V/gain in unipolar mode or ±3.75 V/gain in bipolar mode. REFERENCE The ADC has a fully differential input capability for the reference channel. In addition, the user has the option of selecting one of two external reference options (REFIN1(± ...

  • Page 31

    ... AIN1 pin is 2 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7194 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1. 3.75 V. The bipolar/unipolar option is chosen by programming the U/ B bit in the configuration register ...

  • Page 32

    ... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7194 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface is lost due to a software error or a glitch in the system ...

  • Page 33

    ... Single Conversion Mode In single conversion mode, the AD7194 is placed in power- down mode after conversions. When a single conversion is initiated by setting MD2 to 0, MD1 to 0, and MD0 the mode register, the AD7194 powers up, performs a single conversion, and then returns to power-down mode. The on- chip oscillator requires 200 μ ...

  • Page 34

    ... AD7194 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7194 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the commu- nications register, indicating that the next operation is a read of the data register ...

  • Page 35

    ... Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7194 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communi- cations register, the user need only apply the appropriate number ...

  • Page 36

    ... SYNC pin resets the digital filter and the analog modulator and places the AD7194 into a consistent, known state. While the SYNC pin is low, the AD7194 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again ...

  • Page 37

    ... CALIBRATION The AD7194 provides four calibration modes that can be pro- grammed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. ...

  • Page 38

    ... The gain error of the AD7194 is factory calibrated at a gain of 1 with power supply at ambient temperature. Following this calibration, the gain error is ±0.001%, typically Table 27 shows the typical uncalibrated gain error for the different gain settings ...

  • Page 39

    ... DIGITAL FILTER The AD7194 offers a lot of flexibility in the digital filter. The device has five filter options. The device can be operated with sinc or sinc filter, chop can be enabled or disabled, and zero latency can be enabled. Finally, an averaging block can be included after the sinc filter, which gives a fast settling mode. ...

  • Page 40

    ... AD7194 When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process ...

  • Page 41

    ... Output Data Rate (Hz) Settling Time (ms) 10 300 CHANNEL B CHANNEL A CHANNEL ADC 3 Figure 36. Sinc Channel Change ANALOG INPUT ADC OUTPUT f 1/ ADC Figure 37. Asynchronous Step Change in Analog Input Zero Latency AD7194 . ADC FULLY SETTLED ...

  • Page 42

    ... AD7194 The output data rate equals /(3 × 1024 × FS[9:0]) ADC SETTLE CLK where the output data rate. ADC f is the master clock (4.92 MHz nominal). CLK FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate ...

  • Page 43

    ... Rev Page FILTER) ADC CHOP 3 4 MODULATOR SINC /SINC POST FILTER Figure 43. Chop Enabled 4 Chop 4 filter, the output data rate is equal /(4 × 1024 × FS[9:0]) CLK = 2/f ADC Output Data Rate (Hz) Settling Time (ms) 12.5 160 15 133 AD7194 ...

  • Page 44

    ... AD7194 When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f . ADC CHANNEL A CHANNEL CONVERSIONS Figure 44. Channel Change (Sinc ...

  • Page 45

    ... ADC OUTPUT f 1/ ADC is equal to 3dB = 0.24 × f 3dB ADC 3 Chop Enabled) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 100 FREQUENCY (Hz) 3 Figure 51. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) AD7194 3 Chop Enabled) /2. The ADC 125 150 ...

  • Page 46

    ... AD7194 The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 52 is achieved. The output data rate is unchanged but the 50 Hz/60 Hz ± rejection improves typically. ...

  • Page 47

    ... FREQUENCY (Hz) Figure 58. Filter Response for Average + Decimate Filter 4 (Sinc Filter, FS[9:0] = 30, Average by 16) 0 –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (Hz) Figure 59. Filter Response for Average + Decimate Filter 4 (Sinc Filter, FS[9:0] = 96, Average by 16) AD7194 120 150 120 150 ...

  • Page 48

    ... AD7194 3 FAST SETTLING MODE (SINC FILTER) In fast settling mode, the settling time is close to the inverse of the first filter notch. Therefore, the user can achieve 50 Hz and/ rejection at an output data rate close to 1/ 1/60 Hz. The settling time is equal to 1/output data rate. Therefore, the conversion time is constant when converting on a single channel or when converting on several channels ...

  • Page 49

    ... Figure 66. Filter Response for Average + Decimate Filter Rev Page AD7194 120 FREQUENCY (Hz) 3 (Sinc Filter, FS[9:0] = 30, Average by 16 120 FREQUENCY (Hz) 3 (Sinc Filter, FS[9:0] = 96, Average by 16) ...

  • Page 50

    ... AD7194 FAST SETTLING MODE (CHOP ENABLED) Chop can be enabled in the fast settling mode. With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded ...

  • Page 51

    ... SUMMARY OF FILTER OPTIONS The AD7194 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. 1 Table 36. Filter Summary Filter FS[9: Sinc , Chop Disabled 1 4 Sinc ...

  • Page 52

    ... AD7194 to prevent noise coupling. The power supply lines to the AD7194 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals, ...

  • Page 53

    ... FLOWMETER Figure 67 shows the AD7194 being used in a flowmeter application that consists of two pressure transducers with the rate of flow being equal to the pressure difference. The pressure transducers are arranged in a bridge network and give a differential output voltage between its OUT+ and OUT− ...

  • Page 54

    ... AD7194 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD7194BCPZ −40°C to +105°C 1 AD7194BCPZ-REEL −40°C to +105°C 1 AD7194BCPZ-REEL7 −40°C to +105° RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY ...

  • Page 55

    ... NOTES Rev Page AD7194 ...

  • Page 56

    ... AD7194 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. registered trademarks are the property of their respective owners. D08566-0-10/09(0) Rev Page ...