AD7194 Analog Devices, AD7194 Datasheet - Page 50

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7194
FAST SETTLING MODE (CHOP ENABLED)
Chop can be enabled in the fast settling mode. With chop
enabled, the ADC offset and offset drift are minimized. The
analog input pins are continuously swapped. With the analog
input pins connected in one direction, the settling time of the
sinc filter is allowed and a conversion is recorded. The analog
input pins are then inverted, and another settled conversion
is obtained. Subsequent conversions are averaged so that the
offset is minimized. This continuous swapping of the analog
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input pins and the averaging of subsequent conversions means
that the offset drift is also minimized.
Chopping does not change the output data rate. However, the
settling time equals
Consequently, if chop is enabled, the sinc
is set to 6 and averaging by 16 is enabled, and the output data
rate is equal to 42.1 Hz. Therefore, the conversion time equals
1/42.10 Hz or 23.75 ms and the settling time is equal to 47.5 ms.
t
SETTLE
= 2/f
ADC
4
filter is selected, FS[9:0]