AD7194 Analog Devices, AD7194 Datasheet - Page 37

• Manufacturer Part Number: AD7194
• Description: 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
• Manufacturer: Analog Devices

Specifications of AD7194

• Resolution (bits): 24bit
• # Chan: 8
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Following the one-point calibration, the internal temperature
sensor has an accuracy of ±2°C, typically.
LOGIC OUTPUTS
The AD7194 has four general-purpose digital outputs: P0, P1,
P2, and P3. These are enabled using the GP32EN and GP10EN
bits in the GPOCON register. The pins can be pulled high or
low using the P0DAT to P3DAT bits in the GPOCON register;
that is, the value at the pin is determined by the setting of the
P0DAT to P3DAT bits. The logic levels for these pins are
determined by AV
register is read, Bit P0DAT to Bit P3DAT reflect the actual value
at the pins; this is useful for short-circuit detection.
These pins can be used to drive external circuitry, for example,
an external multiplexer. If an external multiplexer is used to
increase the channel count, the multiplexer logic pins can be
controlled via the AD7194 general-purpose output pins. The
general-purpose output pins can be used to select the active
multiplexer pin. Because the operation of the multiplexer is
independent of the AD7194, the AD7194 modulator and filter
should be reset using the SYNC pin or by a write to the mode or
configuration register each time that the multiplexer channel is
changed.
CALIBRATION
The AD7194 provides four calibration modes that can be pro-
grammed via the mode bits in the mode register. These modes
are internal zero-scale calibration, internal full-scale calibration,
system zero-scale calibration, and system full-scale calibration.
A calibration can be performed at any time by setting the MD2
to MD0 bits in the mode register appropriately. A calibration
should be performed when the gain is changed. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The offset calibration coefficient is subtracted from the result
prior to multiplication by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2
to MD0 bits. The DOUT/ RDY pin and the RDY bit in the
status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding
calibration registers are updated, the RDY bit in the status
register is reset, the DOUT/ RDY pin returns low (if CS is low),
and the AD7194 reverts to idle mode.
DD
rather than by DV
DD
. When the GPOCON
Rev. 0 | Page 37 of 56
During an internal zero-scale or full-scale calibration, the respec-
tive zero input and full-scale input are automatically connected
internally to the ADC input pins. A system calibration,
however, expects the system zero-scale and system full-scale
voltages to be applied to the ADC pins before initiating the
calibration mode. In this way, errors external to the ADC are
removed.
From an operational point of view, treat a calibration like
another ADC conversion. A zero-scale calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/ RDY pin to determine the end of calibration via a
polling sequence or an interrupt-driven routine.
With chop disabled, both an internal zero-scale calibration and
a system zero-scale calibration require a time equal to the settling
time, t
filter).
With chop enabled, an internal zero-scale calibration is not
needed because the ADC itself minimizes the offset continuously.
However, if an internal zero-scale calibration is performed, the
settling time, t
tion. Similarly, a system zero-scale calibration requires a time of
t
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. For a gain of 1, the time required for an
internal full-scale calibration is equal to t
the internal full-scale calibration requires a time of 2 × t
A full-scale calibration is recommended each time the gain of a
channel is changed to minimize the full-scale error.
A system full-scale calibration requires a time of t
chop disabled, the zero-scale calibration (internal or system
zero-scale) should be performed before the system full-scale
calibration is initiated.
SETTLE
to complete.
SETTLE
(4/f
SETTLE
ADC
for the sinc
(2/f
ADC
), is required to perform the calibra-
4
filter and 3/f
SETTLE
ADC
. For higher gains,
for the sinc
SETTLE
AD7194
. With
SETTLE
3
.