The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part NumberLPC1759FBD80
DescriptionThe LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
ManufacturerNXP Semiconductors
LPC1759FBD80 datasheet
 


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NXP Semiconductors
bus during a given data transfer. The SSP supports full duplex transfers, with frames of
4 bits to 16 bits of data flowing from the master to the slave and from the slave to the
master. In practice, often only one of these data flows carries meaningful data.
7.18.1 Features
Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
2
7.19 I
C-bus serial I/O controllers
The LPC1759/58/56/54/52/51 each contain two I
2
The I
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
7.19.1 Features
2
I
C1 and I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Both I
mode.
2
7.20 I
S-bus serial I/O controllers (LPC1759/58/56 only)
2
The I
S-bus provides a standard communication interface for digital audio applications.
LPC1759_58_56_54_52_51
Product data sheet
LPC1759/58/56/54/52/51
2
C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
2
C-bus can be used for test and diagnostic purposes.
2
C-bus controllers support multiple address recognition and a bus monitor
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
32-bit ARM Cortex-M3 microcontroller
2
C-bus controllers.
2
C is a multi-master bus and can be
© NXP B.V. 2011. All rights reserved.
2
C-bus).
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