The LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz

LPC1759FBD80

Manufacturer Part NumberLPC1759FBD80
DescriptionThe LPC1759 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
ManufacturerNXP Semiconductors
LPC1759FBD80 datasheet
 


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NXP Semiconductors
Fig 24. SPI slave timing (CPHA = 0)
12. ADC electrical characteristics
Table 17.
ADC characteristics (full resolution)
V
= 2.7 V to 3.6 V; T
=
40
DDA
amb
Symbol
Parameter
V
analog input voltage
IA
C
analog input capacitance
ia
E
differential linearity error
D
E
integral non-linearity
L(adj)
E
offset error
O
E
gain error
G
E
absolute error
T
R
voltage source interface
vsi
resistance
f
ADC clock frequency
clk(ADC)
f
ADC conversion frequency
c(ADC)
[1]
The ADC is monotonic, there are no missing codes.
[2]
The differential linearity error (E
D
[3]
The integral non-linearity (E
L(adj)
appropriate adjustment of gain and offset errors. See
[4]
The offset error (E
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
O
ideal curve. See
Figure
25.
[5]
ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360.
[6]
The gain error (E
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
G
error, and the straight line which fits the ideal transfer curve. See
[7]
The absolute error (E
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
T
ADC and the ideal transfer curve. See
[8]
See
Figure
26.
[9]
The conversion frequency corresponds to the number of samples per second.
LPC1759_58_56_54_52_51
Product data sheet
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
DATA VALID
MISO
DATA VALID
C to +85
C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.
Conditions
) is the difference between the actual step width and the ideal step width. See
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
Figure
25.
Figure
Figure
25.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 March 2011
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
T
t
t
SPICYC
SPICLKH
SPICLKL
t
t
SPIDSU
SPIDH
DATA VALID
t
SPIQV
DATA VALID
Min
Typ
0
-
-
-
[1][2]
-
-
[3]
-
-
[4][5]
-
-
[6]
-
-
[7]
-
-
[8]
-
-
-
-
[9]
-
-
25.
t
SPIOH
002aad989
Max
Unit
V
V
DDA
15
pF
1
LSB
3
LSB
2
LSB
0.5
%
4
LSB
7.5
k
13
MHz
200
kHz
Figure
25.
© NXP B.V. 2011. All rights reserved.
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