ST7LIT15BF0 STMicroelectronics, ST7LIT15BF0 Datasheet - Page 137

• Manufacturer Part Number: ST7LIT15BF0
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT15BF0

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 107. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
OSC
t
t
w(SCKH)
t
w(SCKL)
Symbol
1/t
t
t
t
dis(SO)
t
t
t
t
t
t
su(SS)
t
su(MI)
t
h(MO)
su(SI)
a(SO)
h(SO)
v(MO)
t
t
h(SS)
v(SO)
h(MI)
h(SI)
r(SCK)
f(SCK)
f
MISO
MOSI
c(SCK)
, and T
SCK
SS
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
1)
1)
OUTPUT
INPUT
1)
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
=8MHz, then T
t
t
h(SI)
c(SCK)
t
DD
v(SO)
DD
CPU
,
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable
edge)
CPU
CPU
BIT6 OUT
and 0.7xV
= 1/f
=8MHz
=8MHz
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Conditions
3)
CPU
DD
=125ns and t
BIT1 IN
.
t
h(SO)
su(SS)
(4 x T
t
t
r(SCK)
f(SCK)
f
CPU
see I/O port pin description
0.0625
=550ns
Min
CPU
120
100
100
100
100
100
90
0
0
0
0
LSB IN
/128
) + 50
LSB OUT
t
h(SS)
ST7LITE1xB
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
137/159
note 2
Unit
see
MHz
ns